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Visitor dvk_1
Visitor
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Read/Write PCIe command register values

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Hello Everyone,

 

I am trying to read values of command register using setpci command. 

 

Used below commands respectively to read command register, command_io, command_memory and command_wait fields of command register.

 

setpci  -s 62:00.2 0x04.w

0146

setpci  -s 62:00.2 0x04+01.b

01

setpci  -s 62:00.2 0x04+02.b

10

setpci  -s 82:00.2 0x04+80.b

22

 

Can someone please explain what does the values 01,10, 22 idicate. Aren't these fields single bit and take only 1/0 as the value?

 

I came up with these register addresses from pci_regs.sh

 

#define PCI_COMMAND             0x04    /* 16 bits */

#define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */

#define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */

#define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */

 

Thanks,

Div

 

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
718 Views

Re: Read/Write PCIe command register values

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From the setpci MAN page:

 

+offset is to add an offset (a hex number to the address)

.B, .W, or .L to choose how many bytes (1, 2, or 4) should be transferred.

 

So 0x04.W is simply print the 2 bytes of the Command register

0x04+01.b would be 1 byte @ 0x05 or COMMAND[7:4]   

     in your case - 0x01 - SERR# enable

0x04+02.b would be 1 byte @ 0x06 or STATUS[3:0]

     in your case - 0x10 - bit 4 - Capabilities List (required to be hardwired to 1)

0x04+80.b would be 1 byte @0x84 (a totally different part of the Configuration space register set)

     will be totally device dependent as this would be in the linked list part of Configuration Space, and we would have to know which capability and offset this was related to to decode. 

 

(Bytes, not bits) 

 

I don't see a way in the setpci command to read out individual bit level values.  You will likely need to do the 0x04.w (or COMMAND), and then parse out the individual bit results yourself. 

 

The definition of the individual bits in the command register are called out in the PCI and PCIe Specification.  

 

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2 Replies
Xilinx Employee
Xilinx Employee
719 Views

Re: Read/Write PCIe command register values

Jump to solution

From the setpci MAN page:

 

+offset is to add an offset (a hex number to the address)

.B, .W, or .L to choose how many bytes (1, 2, or 4) should be transferred.

 

So 0x04.W is simply print the 2 bytes of the Command register

0x04+01.b would be 1 byte @ 0x05 or COMMAND[7:4]   

     in your case - 0x01 - SERR# enable

0x04+02.b would be 1 byte @ 0x06 or STATUS[3:0]

     in your case - 0x10 - bit 4 - Capabilities List (required to be hardwired to 1)

0x04+80.b would be 1 byte @0x84 (a totally different part of the Configuration space register set)

     will be totally device dependent as this would be in the linked list part of Configuration Space, and we would have to know which capability and offset this was related to to decode. 

 

(Bytes, not bits) 

 

I don't see a way in the setpci command to read out individual bit level values.  You will likely need to do the 0x04.w (or COMMAND), and then parse out the individual bit results yourself. 

 

The definition of the individual bits in the command register are called out in the PCI and PCIe Specification.  

 

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Visitor dvk_1
Visitor
523 Views

Re: Read/Write PCIe command register values

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Thanks Bethe for your time! Yes, I figured out that bits has to be parsed individually. 

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