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Contributor
Contributor
120 Views
Registered: ‎10-15-2018

Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

Hi,

I would like to perform data transfer between the vc707 eval board and SBC (single board computer) using PCIe. However, I have mistakenly made slight hardware changes to the gtx transceivers wiring in the vc707 eval board, connecting MGTAVTT pin to the GND instead of 1.2V (can be seen on pg 14 of VC707 Schematics). This has probably resulted in the loss of pcie link. I have chipscoped into the LTSSM_state and it has been looping within the compliance state (04 -> 08 -> 09 -> 0A -> 04)

While the board is being re-spun, does using TERM_RCAL_OVRD & TERM_RCAL_CFG attribute a viable solution?

What are the suitable values for TERM_RCAL_OVRD & TERM_RCAL_CFG needed to ensure that the pcie link is working again, given that the MGTAVTT pin is connected to the GND ?

Appreciate a reply as soon as possible.

 

Thanks

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7 Replies
Xilinx Employee
Xilinx Employee
102 Views
Registered: ‎10-19-2011

Re: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

Hi @aliciachee ,

I am afraid changing the calibration settings will not help you much. Please check with ug476, page 302, what parts are actually running on MGTAVTT. It is not just the calibration and termination. You are probably lucky that you already go past the receiver detection.

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Contributor
Contributor
87 Views
Registered: ‎10-15-2018

Re: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

Hi @eschidl,

Thanks for the reply. I realized that except for this particular section (which I have outlined it in red and attached in this message), all the other parts are connected correctly to MGTAVTT. This particular section can be found on pg 14 of VC707 Schematics, whereby pin A12 & B11 is connected to GND, instead of MGTAVTT.

In this case, will changing the values of TERM_RCAL_OVRD & TERM_RCAL_CFG help in establishing the pcie link?  

Thanks

VC707_FPGA_connection.jpg
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Xilinx Employee
Xilinx Employee
78 Views
Registered: ‎08-07-2007

回复: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

hi @aliciachee 

 

if MGTAVTT is connected to gnd, not only the RCAL fails, but also the overall GTX fails.

Please look at Figure 5-2 in UG476. MGTAVTT is powering lot of circuis. not just the calibration circuit, but also many other circuits.

https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

so tuning the RCAL cannot help in solving the pcie link issue because all GTXs are completely down if MGTAVTT is connected to GND.

 

Thanks,

Boris

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Contributor
Contributor
70 Views
Registered: ‎10-15-2018

回复: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

Hi @borisq ,

I think you misunderstood what I am trying to say. From the diagram below, I have mistakenly connected pin A12 & B11, that consists the R165 resistor to GND instead of MGTAVTT. Hence my question is:

will changing the values of TERM_RCAL_OVRD & TERM_RCAL_CFG help in establishing the pcie link?  

Thanks

VC707_FPGA_connection.jpg
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Xilinx Employee
Xilinx Employee
65 Views
Registered: ‎08-07-2007

回复: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

hi @aliciachee 

 

ok. thanks for clarification.

did you measure the impedance between rxp and rxn after power on and configuration?

what is the resistance?

 

Thanks,

Boris

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Contributor
Contributor
54 Views
Registered: ‎10-15-2018

回复: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

Hi @borisq ,

I measure the resistance between rxp and rxn before power on and configuration, and after power on and configuration. Following are the values:

Before power on & configuration: 150 ‎Ω

After power on & configuration : 94.3 ‎Ω

Any idea if changing the values of TERM_RCAL_OVRD & TERM_RCAL_CFG help in establishing the pcie link? 

Thanks

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Xilinx Employee
Xilinx Employee
47 Views
Registered: ‎10-19-2011

回复: Setting a suitable value for .TERM_RCAL_CFG & .TERM_RCAL_OVRD for pcie GTX transceivers

Hi @aliciachee ,

the values tell that the termination changes during config. But they are not too far off to 100Ohm. You can try to change the settings with overriding the RCAL.

But my concern would still be the connection to ground, you probably have a current draw between MGTAVTTRCAL and MGTAVTT. Not sure what effect this will have on the device. It might get destroyed at some stage. That would depend on how much current is going there.

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