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Observer fsgaglione
Observer
340 Views
Registered: ‎12-27-2018

Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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Hello,

I'm trying to simulate an example project generated by the IP "DMA/Bridge Subsystem for PCI Express (PCIe)" with a cadence tool.

The project uses an Endpoint in which an "m_axi model" module writes it via PCIe Bridge. The module performs a writing and then a reading at the same address, but in my simulation I added an additional writing and reading.
The new writing is performed in the same address but with a different data. When the reading from that address is carried out again, the data reported refers to the first writing:

Write1:

s_axib_awaddr = 40'h00_B000_0080; s_axib_wdata = 128'hC4C4C4C4

Read1:

s_axib_araddr = 40'h00_B000_0080; s_axib_rdata = 128'hC4C4C4C4

Write2:

s_axib_awaddr = 40'h00_B000_0080; s_axib_wdata = 128'h12341234

Read2:

s_axib_araddr = 40'h00_B000_0080; s_axib_rdata = 128'hC4C4C4C4

wr.PNG

is this mismatch due to the endpoint because it is just an example or did I miss something?

Thanks in advance.

 

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
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1 Solution

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Xilinx Employee
Xilinx Employee
227 Views
Registered: ‎07-26-2012

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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Thak you very much for giving me the information. I understood your IP configuration and confirmed the behavior that you saw. This is an error in the memory access logic connected to the simulation model of EP.

Once the EP memory is accessed, "dword_count" value in the pio_ep_mem_acess module is incremented, but this value is not returned to the initial value at the second access. As a simple modification, clear the value under PIO_MEM_ACCESS_WR_RST state. I will file a change request against this behavior.

 

// Example

 PIO_MEM_ACCESS_WR_RST : begin

            dword_count <=#TCQ 1'b0; // reset "dword_count" to '0'

 

PCIe_brdge_twice_wr_rd.png

6 Replies
Xilinx Employee
Xilinx Employee
303 Views
Registered: ‎07-26-2012

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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Could you tell me the IP version/Device being used?

If the Read request was received after the second write was reliably saved on the RP side, there is a possibility of limitation of the RP model. The RP model attached to IP supports only simple transactions, and some of them can not correctly return completion from EP (DUT).

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Observer fsgaglione
Observer
294 Views
Registered: ‎12-27-2018

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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Hi kurihara,

the version of the DMA/Bridge Subsystem for PCI Express (PCIe) is 4.1 (Rev. 1) while the EP isn't an IP but in the example project it is a simulation source.

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
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Xilinx Employee
Xilinx Employee
281 Views
Registered: ‎07-26-2012

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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As for the point that "the EP isn't an IP ", I am a bit confused. Is the DMA / Bridge Subsystem for PCI Express (PCIe) not generated as an endpoint? Is it Root Port mode?
 
If you could attached the xci file, it is helpful.
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Observer fsgaglione
Observer
254 Views
Registered: ‎12-27-2018

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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Hi kurihara,

I have generated the example (click on "open IP Example Design" ) of the DMA / Bridge Subsystem for PCI Express (PCIe) ver 4.1 as Root Port.

Sorry if I was not clear. I show you the window source:

window.PNG

the IP DMA / Bridge Subsystem for PCI Express (PCIe) is called "xdma_0_i" and it's a root port while the EP are composed of some verilog files situated in a folder called "import". So I thought the EP was not fully implemented being an example.

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
228 Views
Registered: ‎07-26-2012

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

Jump to solution

Thak you very much for giving me the information. I understood your IP configuration and confirmed the behavior that you saw. This is an error in the memory access logic connected to the simulation model of EP.

Once the EP memory is accessed, "dword_count" value in the pio_ep_mem_acess module is incremented, but this value is not returned to the initial value at the second access. As a simple modification, clear the value under PIO_MEM_ACCESS_WR_RST state. I will file a change request against this behavior.

 

// Example

 PIO_MEM_ACCESS_WR_RST : begin

            dword_count <=#TCQ 1'b0; // reset "dword_count" to '0'

 

PCIe_brdge_twice_wr_rd.png

Observer fsgaglione
Observer
217 Views
Registered: ‎12-27-2018

Re: Simulation Xilinx Example DMA/Bridge Subsystem for PCI Express

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Thanks kurihara for your support,

I've modified the status and now the EP respond correctly.

Fabiano Sgaglione
ENG-MNAND DESIGN
NVE MNAND Validation
Micron Technology, Inc.
Email: fsgaglione@micron.com
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