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Visitor bonzo90
Visitor
3,796 Views
Registered: ‎01-03-2017

Spartan-6 Integrated Endpoint Block for PCI Express - PIO example in HW

Hi all,

 

I have an issue with a PIO example of Spartan-6 Integrated Endpoint Block for PCI Express.

I'm trying to test in hardware (Galatea Spartan-6 dev board) the generated PCIe core (only BAR0 enabled, 512b).

The similar core is ready here:

https://github.com/numato/samplecode/tree/master/FPGA/galatea/galateaPCIeGpio 

After generation and implementation of verilog module - I'm running it on HW.

To read and write registers I'm using this app:

https://github.com/billfarrow/pcimem

 

Connection to the PCI endpoint is ready, but I'm still reading the 0xFFFFFFFF on every offset.

Only on 0xFFF offset I'm reading: 0x494350FF

 

Do you have any idea way this happening?

It is rather systems/HW issue? Or rather FPGA bitfiles (from CORE generator 14.7)?

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Visitor bonzo90
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3,718 Views
Registered: ‎01-03-2017

Re: Spartan-6 Integrated Endpoint Block for PCI Express - PIO example in HW

Unfortunately I don't have edit option in my post.

 

I noticed that BAR0 is not mapped at all.

dmesg reports only:

 

ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e])

 

pci 0000:00:1c.1: PCI bridge to [bus 02]

pci 0000:00:1c.1: bridge window [mem 0xf0600000-0xf06fffff]

 

pci 0000:02:00.0: [10ee:0007] type 00 class 0x050000

pci 0000:02:00.0: reg 0x10: [mem 0xf0600000-0xf06001ff]

pci 0000:02:00.0: supports D1 D2

pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot

pci 0000:02:00.0: System wakeup disabled by ACPI

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