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Explorer
Explorer
12,097 Views
Registered: ‎12-01-2010

Trouble with 64-bit address Memory Write TLP

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I have a fully running DMA engine sending posted  32-bit (3DW) memory writes (MWr) to PC memory.

I can send any payload length up to 256 bytes (Xilinx 8x PCIe limitation) with out issue.

 

This is via PCI Express operating on a VC707 Xilinx Development board.

 

When i attempt to send to a 64-bit address, however, the TLPs are dropped and never arrive.  I have checked and re-checked the headers, and they should be fine, so i have no idea what is causing this!

 

I change the Format bits from 10b to 11b to go from 3DW to 4DW.  My length and byte enables seem to be correct.  Is there something else that needs to be set, or something else that i'm missing?

 

 

 

Example 4DW transaction:  (that is not working)

------------------------------------

2 data words (xAAAAAAAA and xBBBBBBBB) sent to address upper x0000000 lower x12345678

requester ID: xCCCC

 

My 6 DWs are:

x 60000002

x CCCC00FF

x 00000000

x 12345678

x AAAAAAAA

x BBBBBBBB

 

Can anyone see anything wrong with what i'm doing here?!

 

Once again, all 32-bit addressed (3DW) transactions work fine!

 

Thanks in advance!

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Explorer
Explorer
18,756 Views
Registered: ‎12-01-2010

Re: Trouble with 64-bit address Memory Write TLP

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I have figured out my own problem.

According to the PCIe spec,

A transfer below 4 GB must use a 3 DWord header, a transfer
above 4 GB must use a 4 DWord header. IE. a four dword header wth address[63:32]
set to zero is invalid!

 

So with the example below, all that was needed to get the 64-bit DMA to work was to change the 3rd DW from all zeroes to something else.

 

 

More detailed information, including driver development, can be found at this forum:

http://www.fpgarelated.com/comp.arch.fpga/thread/93442/dma-operation-to-64-bits-pc-platform.php

1 Reply
Highlighted
Explorer
Explorer
18,757 Views
Registered: ‎12-01-2010

Re: Trouble with 64-bit address Memory Write TLP

Jump to solution

I have figured out my own problem.

According to the PCIe spec,

A transfer below 4 GB must use a 3 DWord header, a transfer
above 4 GB must use a 4 DWord header. IE. a four dword header wth address[63:32]
set to zero is invalid!

 

So with the example below, all that was needed to get the 64-bit DMA to work was to change the 3rd DW from all zeroes to something else.

 

 

More detailed information, including driver development, can be found at this forum:

http://www.fpgarelated.com/comp.arch.fpga/thread/93442/dma-operation-to-64-bits-pc-platform.php