12-17-2017 09:12 PM
I am new to PCIe.
I created a basic block design containing DMA/Bridge Subsystem with PCIe and MIG 7 series. I connected the resets to active HIGH push buttons.
I used the PCIe and DDR3 constraints from VC 707 manual (UG 885 document).
I generated the bitstream, programmed VC 707 and rebooted the system to check if the PCIe core in FPGA is enumerated during boot in BIOS settings.
The BIOS settings show the PCIe slots are "not populated".
lspci -x -d options also don't work (probably because it isn't enumerated)
Am I doing something wrong ?
How do I get it to work ?
I'm using Vivado 2017.2 and Ubuntu 16.04.3 LTS (kernel 4.10.0-42-generic)
01-22-2018 10:31 AM
12-17-2017 10:21 PM
@jagannath You should make sure you power cycle your host. PCI-e does not like live programming.
Also make sure you are not placing the board on a restricted slot - VGA for example - and that your motherboard has enough lanes to support it. Some motherboards show what is populated on each slot and the speed/version of pci express it is using.
Example - ASUS
12-17-2017 11:53 PM - edited 12-17-2017 11:54 PM
Here are my observations
1. First, I created a custom block design using DMA Subsystem for PCIe and MIG 7 series and I programmed the bitstream onto VC 707. It did not get enumerated during boot.
2. Then I created an example IP design for DMA Subsystem for PCIe and I programmed the bitstream onto VC 707. It did not get enumerated during boot.
3. Lastly, I created an example IP design for 7 Series Integrated Block for PCI Express and I programmed the bitstream onto VC 707. It successfully got enumerated during boot.
So there must be something wrong I am doing with DMA Subsystem for PCIe or my custom block design. I can't quite point my finger at it yet.
How is that the bitstream for example design for 7 Series Integrated Block for PCI Express is getting generated even though the top-level ports like pci_exp_txn ( and rxn, txp, rxp) are not mentioned in the constraint file ?
(The constraint file in the default example design has location constraint only for sys_clk_p)
12-18-2017 01:08 AM
Answering my own question.. it turns out the eval boards like VC 707 have XML files (present in Vivado installation folder) which have the requisite constraints contained in them. I guess example IP designs would pick the constraints directly from those files.
12-19-2017 03:02 AM
I made an example design with the XDMA IP using all default settings. It still didn't get detected at boot.This is happening only with DMA Subsystem IP.
The other two IPs (7 Series Integrated Block for PCIe and AXI Memory Mapped to PCIe) got enumerated.
I'm using Vivado 2017.2. According to IP Changelog, XDMA supports PCIe gen2 devices too. I'm unable to figure out what is happening. Could someone please guide me ?
01-22-2018 10:31 AM