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1,734 Views
Registered: ‎12-30-2008

VC707 PCI Express DMA example project using Vivado 2017.4.1

I've created a simple VC707 PCI Express DMA project using Vivado 2017.4, but get the following errors.

[DRC REQP-52] connects_GTGREFCLK_ACTIVE: GTXE2_CHANNEL cell vc707_pcie_dma_design_i/xdma_0/inst/vc707_pcie_dma_design_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.

[DRC REQP-56] connects_GTGREFCLK_ACTIVE: GTXE2_COMMON cell vc707_pcie_dma_design_i/xdma_0/inst/vc707_pcie_dma_design_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtx_common.gtxe2_common_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.


The steps that I took to create this project were as follows:

01. Create a new project for the VC707 evaluation board, using Vivado 2017.4.1

02 From the IP catalog, instantiate an instance of the DMA/Bridge Subsystem for PCI Express v4.0 Rev1

      Customize the IP core to enable x8 lanes, 5.0 GT/s, Ref Clock Frequency 100MHz, PCIe Block Location X1Y0, Functional Mode: DMA Basic

      Perform an out-of-context module run for the IP core.

03. Create a new block diagram.

    Add the xdma_0 instance to the block diagram.
    Add a new clocking wizard and feed a 100MHz reference clock (clk_out1) to the sys_clk of the xdma_0 instance.
    Run connection automation wizard on the design to complete it.

04. Create a new constraints file vc707_pcie_dma_ref_board.xdc with the following content:

##-----------------------------------------------------------------------------
##
## Project    : Xilinx VC707 PCI Express DMA
## File       : vc707_pcie_dma_ref_board.xdc
## Version    : 1.0
##-----------------------------------------------------------------------------
#
###############################################################################
# User Configuration
# Link Width   - x5
# Link Speed   - gen2
# Family       - virtex7
# Part         - xc7vx485t
# Package      - ffg1761
# Speed grade  - -2
# PCIe Block   - X0Y0

###############################################################################
# User Physical Constraints
###############################################################################
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property CONFIG_MODE BPI16 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]

###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
# Some 7 series devices do not have 3.3 V I/Os available.
# Therefore the appropriate level shift is required to operate
# with these devices that contain only 1.8 V banks.
#


###############################################################################
# Physical Constraints
###############################################################################
#
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-7 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-7 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
#

set_property LOC E19 [get_ports sys_clk_p_IBUF_inst]

set_property LOC E18 [get_ports sys_clk_n_IBUF_inst]

######################################################################


05. Right click the block diagram and create the HDL wrapper.

06. Generate the project tcl file.

    write_project_tcl or File > Write Project TCL

07. Run synthesis.

08. Run implementation.

This results in the following errors

[DRC REQP-52] connects_GTGREFCLK_ACTIVE: GTXE2_CHANNEL cell vc707_pcie_dma_design_i/xdma_0/inst/vc707_pcie_dma_design_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.


[DRC REQP-56] connects_GTGREFCLK_ACTIVE: GTXE2_COMMON cell vc707_pcie_dma_design_i/xdma_0/inst/vc707_pcie_dma_design_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtx_common.gtxe2_common_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.


How can I fix this? I know what one possible work around is to disable the DRC REQP-56 check, since it was change from a warning to a severe error a while back, in an earlier vivado release.

 

I would like to know the proper way to fix this error, without disabling this warning. I am using an external clock derived from the clocking wizard. Is there another clocking resource that I should be using that is available on the VC707 board, to make this error go away?

I've attached the project tcl and the pdf of the block diagram.

 

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5 Replies
Moderator
Moderator
1,692 Views
Registered: ‎02-16-2010

Re: VC707 PCI Express DMA example project using Vivado 2017.4.1

You should use on-board clock as an input to the design. I find the PCIe edge connector on VC707 is connected to quad 115 and slot clock is coming on AB8/AB7 pins. Try to assign the sys_clk input to these pins and check.
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1,589 Views
Registered: ‎12-30-2008

Re: VC707 PCI Express DMA example project using Vivado 2017.4.1

sys_clk input on the xdma_0 side requires a differential input signal.

 

Can I connect it directly to an external port called pcie_refclk and specify pcie_refclk_p and pcie_refclk_n in the xdc file?

 

This doesn't seem to work:

 

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 34 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pcie_refclk.

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 34 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: pcie_refclk.
# PCIE_PERST_B PERST Integrated Endpoint block reset signal
set_property LOC AV35 [get_ports pcie_perst_ls]
set_property IOSTANDARD LVCMOS18 [get_ports pcie_perst_ls]

# MGT_BANK_114 GTXE2_CHANNEL_X1Y5 PCIe6
set_property LOC IBUFDS_GTE2_X1Y5 [get_cells refclk_ibuf]

# Si5324_OUT_C_P REFCLK+ Integrated EndPoint block differential clock pair from PCIe
set_property LOC AB8 [get_ports pcie_refclk_p]

# Si5324_OUT_C_N REFCLK- Integrated EndPoint block differential clock pair from PCIe
set_property LOC AB7 [get_ports pcie_refclk_n]

001-xdma_0.png

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1,672 Views
Registered: ‎12-30-2008

Re: VC707 PCI Express DMA example project using Vivado 2017.4.1

Should I connect the sys_clk differential input signal for xdma_0 :

a. directly, or

b. using a utility buffer, or

c. using a clocking wizard?

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Highlighted
1,658 Views
Registered: ‎12-30-2008

Re: VC707 PCI Express DMA example project using Vivado 2017.4.1

002-xdma-with-mig.pngThe only way I was able to get the design to generate a bitstream without errors was to use a utility buffer and configure it to accept a differential input signal and output that to sys_clk of the xdma.

 

However, lscpi doesn't show that PCIe device endpoint after performing a warm reboot.

 

[I've already tried the xdma open ip example design, which uses block ram. I'm trying to get an example working using a block diagram and MIG.]

 

Q001: What should I do to get this design working, so that I can atleast detect the board using lspci?

 

Here are my constraints:

 

#########################################################################################################################
# User Constraints
#########################################################################################################################
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property CONFIG_MODE BPI16 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]

###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

# USER LINK UP = led_2
set_property LOC AR37 [get_ports led_user_lnk_up]
set_property IOSTANDARD LVCMOS18 [get_ports led_user_lnk_up]

set_false_path -to [get_ports -filter {NAME=~led_*}]

###############################################################################
# Physical Constraints
###############################################################################


#
# System Reset Signal.
#
set_property IOSTANDARD LVCMOS18 [get_ports sys_rst]
set_property PULLUP true [get_ports sys_rst]
set_property LOC AV35 [get_ports sys_rst]

#
# System Clock
#

# SYSCLK_P
set_property LOC E19 [get_ports sysclk_p]
set_property IOSTANDARD LVDS [get_ports sysclk_p]

# SYSCLK_N
set_property LOC E18 [get_ports sysclk_n]
set_property IOSTANDARD LVDS [get_ports sysclk_n]


# MGT_BANK_114 GTXE2_CHANNEL_X1Y5 PCIe6
set_property LOC IBUFDS_GTE2_X1Y5 [get_cells refclk_ibuf]

# Si5324_OUT_C_P REFCLK+ Integrated EndPoint block differential clock pair from PCIe
set_property LOC AB8 [get_ports pcie_refclk_p]

# Si5324_OUT_C_N REFCLK- Integrated EndPoint block differential clock pair from PCIe
set_property LOC AB7 [get_ports pcie_refclk_n]

 

Q002: Is there a way to directly connect output of the utility buffer IBUF_DS_ODIV2[0:0] to the sys_clk input of the mig7, instead of having two separate clock domains?

 

At the moment, the VC707 run automation wizard does really work with Vivado 2017.4 for an PCI Express DMA design with MIG, out of the box.

 

 

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1,632 Views
Registered: ‎12-30-2008

Re: VC707 PCI Express DMA example project using Vivado 2017.4.1

I managed to get it working now. For Virtex-7 devices, the output of the utility buffer IBUF_OUT should be connected to sys_clk of the pcie xdma.

 

Additionally, I've learnt that the PCIe reference clock should not be used as sys_clk for DDR3, and should be separate as described in the following post:

https://forums.xilinx.com/t5/Memory-Interfaces/Can-I-use-PCIe-reference-clock-as-sysclk-for-DDR2-controller/td-p/306567

 

003-xdma-with-mig-gpio.png

 

The final set of constraints for this design are as follows:

 

###############################################################################
# User Configuration 
# Link Width   - x8
# Link Speed   - gen2
# Family       - virtex7
# Part         - xc7vx485t
# Package      - ffg1761
# Speed grade  - -2
# PCIe Block   - X0Y0

###############################################################################
#
#########################################################################################################################
# User Constraints
#########################################################################################################################

###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################
create_clock -period 5.000 -name sys_diff_clock [get_ports sys_diff_clock_clk_p]
create_clock -period 10.000 -name pcie_ref [get_ports pcie_ref_clk_p]

###############################################################################
# User Physical Constraints
###############################################################################
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
set_property CONFIG_MODE BPI16 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]

###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

#
# LED Status Indicators for Example Design.
# LED 0-2 should be ON if link is up and functioning correctly
# LED 3 should be blinking if user applicaiton is receiving valid clock
#

# SYS RESET = led_0
#set_property LOC AM39 [get_ports led_0]
#set_property IOSTANDARD LVCMOS18 [get_ports led_0]

# USER RESET = led_1
#set_property LOC AN39 [get_ports led_1]
#set_property IOSTANDARD LVCMOS18 [get_ports led_1]

# USER LINK UP = led_2
set_property LOC AR37 [get_ports led_user_lnk_up]
set_property IOSTANDARD LVCMOS18 [get_ports led_user_lnk_up]

# USER CLK HEART BEAT = led_3
#set_property LOC AT37 [get_ports led_3]
#set_property IOSTANDARD LVCMOS18 [get_ports led_3]

set_false_path -to [get_ports -filter {NAME=~led_*}]

###############################################################################
# Physical Constraints
###############################################################################

#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
# Some 7 series devices do not have 3.3 V I/Os available.
# Therefore the appropriate level shift is required to operate
# with these devices that contain only 1.8 V banks.
#
set_property IOSTANDARD LVCMOS18 [get_ports sys_rst]
set_property PULLUP true [get_ports sys_rst]
set_property LOC AV35 [get_ports sys_rst]

set_false_path -from [get_ports sys_rst]

#
# SYS Clock
#

# SYS_CLK_P
set_property LOC E19 [get_ports sys_diff_clock_clk_p]
set_property IOSTANDARD LVDS [get_ports sys_diff_clock_clk_p]

# SYS_CLK_N
set_property LOC E18 [get_ports sys_diff_clock_clk_n]
set_property IOSTANDARD LVDS [get_ports sys_diff_clock_clk_n]

#
# PCIe Reset Signal. Same as SYS Reset Signal.
# Refer UG885, page 36
#

# PCIE_PERST_B PERST Integrated Endpoint block reset signal
#set_property LOC AV35 [get_ports pcie_perst_ls]
#set_property IOSTANDARD LVCMOS18 [get_ports pcie_perst_ls]

#
# PCIe Reference Clock for MGT_BANK_114.
# The VC707 board includes a Silicon Labs Si5324 jitter attenuator U24 on the back side of the
# board. FPGA user logic can implement a clock recovery circuit and then output this clock
# to a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin AW32 and
# REC_CLOCK_C_N, FPGA U1 pin AW33) for jitter attenuation. The jitter attenuated clock
# (Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTX Quad 114
# inputs MGTREFCLK0P (FPGA U1 pin AD8) and MGTREFCLK0N (FPGA U1 pin AD7). 
# Refer UG885, page 31, 35,36 
#

# MGT_BANK_114 GTXE2_CHANNEL_X1Y5 PCIe6
#set_property LOC IBUFDS_GTE2_X1Y5 [get_cells refclk_ibuf]

# Si5324_OUT_C_P REFCLK+ Integrated EndPoint block differential clock pair from PCIe
set_property LOC AB8 [get_ports pcie_ref_clk_p]

# Si5324_OUT_C_N REFCLK- Integrated EndPoint block differential clock pair from PCIe
set_property LOC AB7 [get_ports pcie_ref_clk_n]

led3 should light up immediately upon programming the board and lspci should register the board after a warm reboot, as follows:

 

01:00.0 Serial controller: Xilinx Corporation Device 7028

 

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