02-24-2017 09:56 AM
I've been following PG239 (Oct 5th 2016), trying to generate a PCI Express PHY IP core. The documentation states that for Ultrascale+ devices only ZU9EG and VUS3P are enabled; and for Ultrascale devices only devices KU040, KU115 and VU440/VU440ES2 are enabled. In addition to this in the AR66988:
it states that the following :
Added xcku115 device support
Added Gen4 Support for UltraScale+ devices xcvu3p-ffvc1517 and xczu9eg-ffvb1156
Using Vivado 2016.4 I have tried to generate the PHY IP using the IP Catalogues "UltraScale FPGA Transceiver Wizard" for any of these devices (i.e. "IP Catalogue" -> "FPGA Features and Design" -> "IO Interfaces" -> "UltraScale FPGAs Transceiver Wizard") I do not get an option under the "Basic" -> "Transceiver configuration present" as the documentation suggests I should.
Could you advise how to do this please.
03-16-2017 03:40 AM
You have to search for PCIE rather transceiver..Please find the snapshot
Moreover Gen4 can be enabled in US+ cores by running this command in tcl console..
Usage: set_property -dict [list CONFIG. <Property Name> <Property Value> [get_ips <Ip Name>]
Then, when you go to generate a core, you should see Gen4
08-16-2017 12:00 AM
I am using Virtex-UltraScale VCU118 Evaluation Platform (xcvu9p-flga2104-2L-e-es1) board. I need a PCIe PHY IP (PIPE interface on one end and serial line on the other) for my FPGA design implementation. I tried searching for 'pcie' in the IP catalog. Attached snapshot shows the results. I do not see the 'PCIe PHY IP' available for my board (it's gryaed out).
May I know if I need to update my vivado tools to any later version or is there any other way to get it?
Thanks in advance for your help.
09-08-2017 07:01 AM
09-08-2017 11:04 AM
Thanks Gareth. I did the same thing for my design as well. I generated the PCIe PHY IP for xcvu3 part and then used the generated RTL files (which are generic) for my design implementation on xcvu9p part.
09-21-2017 03:59 AM
@pankaj11 that's great news and I am happy I could help you. Can you provide kudos to my post for its help to you?
09-21-2017 04:00 AM
@dwp I believe my post clarifies this. Can you provide kudos if this is the case and mark it as an accepted solution?
11-02-2018 11:09 AM
I did the same to generate a GTH PHY for the ZCU106 board(has xczu7ev-ffvc1156 device). After generating the IP for xczu9ev device I ported all the IP generated source files to my design and run the synthesis. Synthesis seems fine but the timing summary shows the frequency of all the output clocks like TXOUTCLK, pipe clock, user clock as double than the expected. I generated the PHY targeting x4 Gen2 PCIe, so the pipe clock should be 250 MHz but the timing shows as 500 Mhz. Could you please clarify this and help me to set up the PHY right? Thank you.