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Visitor dwp
Visitor
3,672 Views
Registered: ‎08-23-2012

Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

Hello Xilinx,

 

I've been following PG239 (Oct 5th 2016), trying to generate a PCI Express PHY IP core. The documentation states that for Ultrascale+ devices only ZU9EG and VUS3P are enabled; and for Ultrascale devices only devices KU040, KU115 and VU440/VU440ES2 are enabled. In addition to this in the AR66988:

 

     https://www.xilinx.com/support/answers/66988.html

 

 it states that the following :

 

Added xcku115 device support
Added Gen4 Support for UltraScale+ devices xcvu3p-ffvc1517 and xczu9eg-ffvb1156

 

Using Vivado 2016.4 I have tried to generate the PHY IP using the IP Catalogues "UltraScale FPGA Transceiver Wizard" for any of these devices (i.e. "IP Catalogue" -> "FPGA Features and Design" -> "IO Interfaces" -> "UltraScale FPGAs Transceiver Wizard") I do not get an option under the "Basic" -> "Transceiver configuration present" as the documentation suggests I should.

 

Could you advise how to do this please.

 

Thanks

 

Dave

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8 Replies
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Xilinx Employee
Xilinx Employee
3,382 Views
Registered: ‎11-25-2015

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

hi @dwp,

 

You have to search for PCIE rather transceiver..Please find the snapshot

 

Moreover Gen4 can be enabled in US+ cores by running this command in tcl console..
 
Usage: set_property -dict [list CONFIG. <Property Name> <Property Value> [get_ips <Ip Name>]

 

Then, when you go to generate a core, you should see Gen4

 

Thanks,

Sethu


 

 

PCIe PHY IP.JPG
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Visitor pankaj11
Visitor
2,583 Views
Registered: ‎08-15-2017

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

Hi,

 

I am using Virtex-UltraScale VCU118 Evaluation Platform (xcvu9p-flga2104-2L-e-es1) board. I need a PCIe PHY IP (PIPE interface on one end and serial line on the other) for my FPGA design implementation. I tried searching for 'pcie' in the IP catalog. Attached snapshot shows the results. I do not see the 'PCIe PHY IP' available for my board (it's gryaed out).

 

May I know if I need to update my vivado tools to any later version or is there any other way to get it?

 

Thanks in advance for your help.

 

-Pankaj

 

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Moderator
Moderator
2,433 Views
Registered: ‎06-29-2011

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

Hi @pankaj11,

 

The main purpose of PCIe PHY IP is to deliver the PHY wrappers. In PHY IP, few devices are supported such the the PHY wrappers can be generated for every GT variant in US/US+ family. These generated wrappers can easily be ported to other devices.


For ex. As ZU7EV device has GTs of type GTH, the GTH wrappers can be generated using ZU9EG-ffvb1156 part. These generated wrapper files can be added the ZU7EV design.

 

The above explanation is also mentioned in PG239.

 

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Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution.

--------------------------------------------------------------------------------------------

 

Kind regards,
Gareth

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Don’t forget to reply, kudo, and accept as solution.
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Kind regards,
Gareth
Visitor pankaj11
Visitor
2,427 Views
Registered: ‎08-15-2017

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

Thanks Gareth. I did the same thing for my design as well. I generated the PCIe PHY IP  for xcvu3 part and then used the generated RTL files (which are generic) for my design implementation on xcvu9p  part.

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Moderator
Moderator
2,326 Views
Registered: ‎06-29-2011

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

@pankaj11 that's great news and I am happy I could help you. Can you provide kudos to my post for its help to you?

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Don’t forget to reply, kudo, and accept as solution.
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Kind regards,
Gareth
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Moderator
Moderator
2,324 Views
Registered: ‎06-29-2011

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

@dwp I believe my post clarifies this. Can you provide kudos if this is the case and mark it as an accepted solution?

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth
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Visitor anben1992
Visitor
651 Views
Registered: ‎11-02-2018

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

Hi Gareth,

 

I did the same to generate a GTH PHY for the ZCU106 board(has xczu7ev-ffvc1156 device). After generating the IP for xczu9ev device I ported all the IP generated source files to my design and run the synthesis. Synthesis seems fine but the timing summary shows the frequency of all the output clocks like TXOUTCLK, pipe clock, user clock as double than the expected. I generated the PHY targeting x4 Gen2 PCIe, so the pipe clock should be 250 MHz but the timing shows as 500 Mhz. Could you please clarify this and help me to set up the PHY right? Thank you.

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Visitor anben1992
Visitor
276 Views
Registered: ‎11-02-2018

Re: Vivado 2016.4 unable to generate PCI Express PHY IP fro any device.

The issue was resolved by selecting CPLL instead of the default QPLL.

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