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Observer cstephan
Observer
130 Views
Registered: ‎04-02-2019

Vivado 2018.3 - Configuring DMA/Bridge Subsystem for PCIe (XDMA) at 5.0 GT/s fails when targeting xqzu19eg-ffrc1760-1M-m device

The DMA/Bridge Subsystem for PCIe (XDMA) can be configured at 2.5, 5.0, or 8.0 GT/s if the Vivado project targets the xczu7ev-ffvc1156-2-e device.

When targeting the xqzu19eg-ffrc1760-1M-m device, the configuration does not complete, and the following errors appear in the Tcl console window:

Targeting an startgroup
set_property -dict [list CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} CONFIG.axi_data_width {64_bit} CONFIG.axisten_freq {250} CONFIG.pf0_device_id {9124} CONFIG.plltype {QPLL1} CONFIG.PF0_DEVICE_ID_mqdma {9124} CONFIG.PF2_DEVICE_ID_mqdma {9124} CONFIG.PF3_DEVICE_ID_mqdma {9124}] [get_bd_cells xdma_0]
INFO: [Device 21-403] Loading part xqzu19eg-ffrc1760-1M-m
xit::create_sub_core: Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 3198.914 ; gain = 1071.605
ERROR: [IP_Flow 19-3461] Value '16' is out of the range for parameter 'User data width(TX_USER_DATA_WIDTH)' for IP 'zynq_ultra_ps_xdma_0_1/zynq_ultra_ps_xdma_0_1_pcie4_ip/zynq_ultra_ps_xdma_0_1_pcie4_ip_gt' . Valid values are - 32, 64
ERROR: [IP_Flow 19-3461] Value '16' is out of the range for parameter 'User data width(RX_USER_DATA_WIDTH)' for IP 'zynq_ultra_ps_xdma_0_1/zynq_ultra_ps_xdma_0_1_pcie4_ip/zynq_ultra_ps_xdma_0_1_pcie4_ip_gt' . Valid values are - 32, 64
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.3/data/ip/xilinx/pcie4_uscale_plus_v1_3/elaborate/gtwizard_elaborate_uscale_plus_v1_3.xit': ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'zynq_ultra_ps_xdma_0_1/zynq_ultra_ps_xdma_0_1_pcie4_ip'. Failed to generate 'Elaborate Sub-Cores' outputs:
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.3/data/ip/xilinx/xdma_v4_1/subcore/pcie_core_elaborate.xit': ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'xdma_0'. Failed to generate 'Elaborate Sub-Cores' outputs:
ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'zynq_ultra_ps_xdma_0_1_pcie4_ip'. IP name 'zynq_ultra_ps_xdma_0_1_pcie4_ip' is already in use in this project. Please choose a different name.

CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.3/data/ip/xilinx/xdma_v4_1/subcore/pcie_core_elaborate.xit': ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'zynq_ultra_ps_xdma_0_1_pcie4_ip'. IP name 'zynq_ultra_ps_xdma_0_1_pcie4_ip' is already in use in this project. Please choose a different name.


ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'xdma_v4_1_2_blk_mem_64_reg_be'. IP name 'xdma_v4_1_2_blk_mem_64_reg_be' is already in use in this project. Please choose a different name.

CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.3/data/ip/xilinx/xdma_v4_1/subcore/blk_mem_gen_elaborate.xit': ERROR: [Common 17-70] Application Exception: Failed to create subcore IP 'xdma_v4_1_2_blk_mem_64_reg_be'. IP name 'xdma_v4_1_2_blk_mem_64_reg_be' is already in use in this project. Please choose a different name.


ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'xdma_0'. Failed to generate 'Elaborate Sub-Cores' outputs:
INFO: [IP_Flow 19-3438] Customization errors found on 'xdma_0'. Restoring to previous valid configuration.
ERROR: [IP_Flow 19-3439] Failed to restore IP 'xdma_0' customization to its previous valid configuration.
INFO: [Common 17-17] undo 'set_property -dict [list CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} CONFIG.axi_data_width {64_bit} CONFIG.axisten_freq {250} CONFIG.pf0_device_id {9124} CONFIG.plltype {QPLL1} CONFIG.PF0_DEVICE_ID_mqdma {9124} CONFIG.PF2_DEVICE_ID_mqdma {9124} CONFIG.PF3_DEVICE_ID_mqdma {9124}] [get_bd_cells xdma_0]'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
endgroup

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Xilinx Employee
Xilinx Employee
69 Views
Registered: ‎07-26-2012

Re: Vivado 2018.3 - Configuring DMA/Bridge Subsystem for PCIe (XDMA) at 5.0 GT/s fails when targeting xqzu19eg-ffrc1760-1M-m device

In Vivado2018.3 I also got some errors ( but not same) during opening the example design aftre ip generation when I use xqzu19eg-ffrc1760-1M-m device as a target. However, 2018.3.1 completed the implementation of the example design without error.

So, if not, could you try Vivado 2018.3.1 ( or 2019.1.1 if possible)? 

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