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Observer wangxiao@skhms
Observer
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Registered: ‎10-30-2018

Where can I find the user-guide document for using the PCIe DRP Port in PCIE4CE

The UG213, Page-388, specifies the pins for the hardware debug port of "PCIe DRP Ports", but it does not have any details about how to use it. I would like to know the register mapping and bits field assignment for this DRP port, so that I will be able to re-configurate the parameter settings for PL_LINK_CAP_MAX_LINK_WIDTH and PL_LINK_CAP_MAX_LINK_SPEED in run-time.

Thanks,

Xiao

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