12-09-2016 03:23 AM
Host: Ubuntu 16.4 LTS (4.4.0)
Lane Width: x8
Link Speed: 2,5GT/s
Reference clock Frequency: 100MHz
Vivado version: 2016.03
I have a custom board and I need to implement an PCIe endpoint with DMA.
At first I use the PCIe Axi memory mapped endpoint (PG055) with the cdma unit (PG034).
Under Linux (Ubuntu) I can see the endpoint (lspci) and writing/reading data to/from a Block Memory work.
As a second step I want to check the DMA Subsystem (xdma [PG195]).
The Problem is that the Hostsystem hang up in the Boot Process (Black screen not text).
I use a clear Ubuntu.
I use for both endpoint the default value for Vendor and Device ID.
I have no idea how to fix the problem.
Can some one give me an hind.
12-09-2016 06:14 AM - edited 12-09-2016 06:15 AM
I have also faced similar issue, but not solved yet.
while implementing example design (open example design) in XDMA (dma subsystem for pci express) in KCU105 it works.
but when customized design with some peripherals wont work on XDMA at same board.
This design was tested on CentOS.
12-13-2016 10:28 PM
Since you claim that link is up and ltssm is in normal working condition i believe the issue is mapping related.Please have a look on below description and see if it helps
PCIe example design generated from Vivado 2016.2 and 2016.3 are found to be working fine on KCU105 board with the same XDMA drivers available with AR65444.
However, if the design including XDMA is not directly connected to BRAM like an example design but using AXI interconnect and DDR4 controller for DMA operation, the following issue can be observed with VIVADO 2016.3 when the XDMA driver got loaded
Xdma: module verification failed: signature and/or required key missing - tainting kernel
Following observations can be found when this error message is reported in linux>dmesg
The kernel module is installed correctly and the xmda devices were recognized.
The board is detected as ID8038 with link status 8GT x8
This means that
./load_driver.sh has loaded the driver correctly
. /reg_rw seems working, the provided application
However, . /dma_to_device halts during the operation.
This is observed with Vivado2016.3 design when XDMA connected to an AXI interconnect with other master..
Following is the reason for the observations
When XDMA is alone, there is no AXI Crossbar inside AXI interconnect. It means, XDMA directly accesses DDR4 MIG as long as an address issued by XDMA is within the range of DDR4. However when AXI Crossbar got inserted between DDR4 MIG and XDMA, DDR4 MIG base address (setting under IPI) will change.
With the updated design including AXI crossbar, the DDR4 MIG could have base address starting from 0x0000_0000_8000_0000 (for example) but XDMA application will be trying to access 0x0000_0000_0000_0000. This caused the program halt.
To solve this issue, it is required to ensure XDMA application tries to access the correct addresses with in the address range of MIG..
Thanks and Regards
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12-19-2016 01:23 AM
Thank you for your answer.
I have added a second BRAM and a JATG to AXI Master.
I have used the following Address configuration:
frst BRAM: 0xC000_0000
second BRAM: 0x0000_0000
PCIe to AXI Lite Master (PCIe to AXI Translation 0x0000000000000000)
These changes haven fix my problem. The Linux Host system hangs up during start-up.
01-02-2017 11:02 PM
New year, new information and test.
I test the following option but nothing works.
XDMA with DMA Interfaces option : AXI Stream
- DMA Interfaces option : AXI Memory Mapped
- disable "PCIe to AXI Lite Master Interface"
- disable MSI Capabilities
- disable MSI-X Capability
every thing testet withe Vivado 2016.04.
With a JTAG to AXI Master i have successful write and read to one of the two BRAMs.
01-05-2017 12:26 AM
I got a working version. But only with X4. The following table shows the tested combination.
|Lane Width||Link Speed 2.5GT/s||Link Speed 5.0GT/s|
|X8||works not||works not|
The "AXI Bridge for PCI EXpress v2.8" endpoint work with x8 and 2.5GT/s.
03-08-2017 07:04 PM
I have a similar issue as yours. The PC hangs during booting no matter it is windows7 or ubuntu linux. Have you made any progress regarding to X8 ?
I used the following software and hardware.
HW-KC705 Rev. 1.0
Vivado 2016.4 with and without AR 68512 patch.
The DAM/Bridge subsystem for PCI Express (V3.0) is customized to Gen2 and X8.
AXI-MM 128-bits @ 250MHz. one H2C and one C2H, others are default.
By the way, by the way I can make either Gen1X8 or Gen2X4 boot successfully by set AXI-MM data width to 64-bit. Once I set it to 128-bit, the PC hangs during booting.
03-09-2017 01:27 AM
I think this is a problem in the IP Core and i think the Problem is the AXI MM
If i change the AXI-MM from 128-Bit to 64-Bit the endpoint works withe PIO ans SG.
I hope the Xilinx fix this Problem in the next VIVADO version.