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Visitor joao1996
Visitor
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Registered: ‎10-13-2018

XDMA and DDR4 MIG (S_AXI_CTRL signal)

Hi,

I am using the Vivado IP Integrator to create a block design. My goal is to transfer data between the host machine and VCU1525 DDR4 memory. For that I am using the following IPs: XDMA and DDR4 MIG.

The MIG block has a signal called C0_DDR4_S_AXI_CTRL but I don't know where it should be connected. Right now it is connected to the XDMA M_AXI_LITE interface (address 0x80000000). Is it correct?

Thank you.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

Re: XDMA and DDR4 MIG (S_AXI_CTRL signal)

Please refer to:

Page 111 of PG150 describes as "Table 4-19 lists the AXI4 slave interface specific signals. Clock/reset to the interface is provided from the Memory Controller."

And also, there is "AXI4-Lite Slave Control/Status Register Interface Block" section at page 109 of PG150.

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