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Adventurer
Adventurer
77 Views
Registered: ‎05-03-2018

XDMA higher transfer sizes

Hello,
we are developing a data transfer application via PCI Express in DMA from the Xilinx KC705 Evaluation Board to a PC running Windows 10.
In short, on the PC we have installed the driver provided by Xilinx (called XDMA) able to manage the interaction with PCI Express DMA IP on FPGA.
We have noticed, however, that the driver released by Xilinx for Windows allows a maximum transfer of 1MByte of data,
while we would need higher transfer sizes (32Mbytes).
For this reason we have tried to modify the driver provided to adapt it to our needs,
but not having achieved the desired results, we would need support on the techniques to be followed to do so.

Below are the details of the development system we use:
• for KC705 Evaluation board: Vivado v2018.3
• as a PC card: iBase MI992 Intel® 7th Gen. Core ™ / Xeon® E3 / Celeron® Mini-ITX Motherboard
• operating system (on acquisition PC): Windows 10 Enterprise 2016 LTSB Version 1607
• the KC705 board and the PC board are connected via PCI Express 8 Lane link
• IP DMA / Bridge Subsystem for PCI Express on FPGA has AXI Stream interface

Do you have any documents or suggestion to provide me to resolved this issue ?

Thanks in advance for your help.
Best regards,
Andrea


1 Reply
Observer miguelcosta94
Observer
23 Views
Registered: ‎11-14-2018

Re: XDMA higher transfer sizes

I'm facing a similar problem. I can't read more than 16 MB. Even for reading this amount, I have to previously update a macro in "dma_engine.h" file of XDMA driver (as shown in the figure below). I'm working with an Alveo U200 board in Windows 10 x64.

Have you already figured out how to solve the problem?

Screenshot_2.png

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