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Observer seemasimon
Observer
289 Views
Registered: ‎08-23-2017

Xilinx DMA/Bridge Subsystem for PCI Express and BAR's size

I’m working on a Virtex-7 design with the PCIe DMA/Bridge subsystem.  We are using the Xilinx PCI Express DMA Driver, but it doesn’t see the config BAR unless we reduce the AXI Master BAR to 16KB or less.  Do you know of a limitation to the AXI Master BAR space?  When we program with a build with a 32KB AXI Master BAR, the config BAR doesn’t show up.  When doing “lspci”, it returns all “F”s in the config space.

 

Vivado 2018.2, DMA/Bridge susystem for PCIe (4.1)

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Xilinx Employee
Xilinx Employee
251 Views
Registered: ‎12-10-2013

Re: Xilinx DMA/Bridge Subsystem for PCI Express and BAR's size

Hi @seemasimon,

 

That is often a system dependency (issue).  It's basically that the system may not have enough space available when the card enumerates, and it requires you to reduce the size.  That being said, 16kb is very small - we normally see this hit if the BAR request is up in the GB range, and needs to be reduced to MB.   There may be a secondary issue.  When you do an lspci -vvv on the board - do you see [disabled] on the BAR?

 

 

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