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Adventurer
Adventurer
268 Views
Registered: ‎11-24-2017

ZCU 106 PCIe link speed

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Hello PCIe gurus,

 

I have ZCU106 board where I implemented Xilinx PCIe IP in DMA mode (PG195) with descriptor bypass and AXI-Stream interface. The PCIe IP is configured as End Point, 4-lane, Gen 3.

 

When I connect such configured ZCU106 board with PEX8749 RDK board from Broadcom that is configured as Root Port, the PCIe link is established but it is reported as Gen1, not Gen3.

 

On the other side, when I configure my PCIe IP inside ZCU106 board as 4-lane, Gen2, PCIe link that is established between ZCU106 and PEX8749 RDK boards is properly reported as Gen2.

 

Do you guys have any idea why it was impossible to establish PCIe Gen3 connection between the baords?

 

Thanks in advance for your time and effort.

 

Sincerely,

Bojan.

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1 Solution

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Xilinx Employee
Xilinx Employee
240 Views
Registered: ‎12-10-2013

Re: ZCU 106 PCIe link speed

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Hi @bojankoce,

 

It sounds like there is an issue during Gen3 training which is failing back to Gen1.  (A Gen3 failure will go back to Gen1, it doesn't go to a Gen2 intermediary).  PLX (PEX parts) had some errata with Gen3 training that require adjustments on their side.  I don't have the exact Errata titles, but there was one regarding parity in Gen3 packets and one that was regarding the PLX using only Gen3 coefficients and ignoring the "Use Preset" bit, both of which have caused some interop challenges.  Please check through the errata for your specific part carefully and apply all recommend updates.

 

 I would highly recommend setting the Xilinx IP, Advanced Mode, GT Settings tab to do Auto RX Equalization.  That will help with one of the two above. 


If that doesn't help, then you can insert a JTAG debugger as described in PG195 and capture the data.  If you provide the LTSSM .dat file produced, we can see what phase training is failing at for Gen3.

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3 Replies
Adventurer
Adventurer
251 Views
Registered: ‎11-24-2017

Re: ZCU 106 PCIe link speed

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Could it be that I have on my ZCU106 board an Engineering Sample (ES) of FPGA device that is unable to achieve Gen 3 standards?

 

Sincerely,

Bojan.

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Xilinx Employee
Xilinx Employee
241 Views
Registered: ‎12-10-2013

Re: ZCU 106 PCIe link speed

Jump to solution

Hi @bojankoce,

 

It sounds like there is an issue during Gen3 training which is failing back to Gen1.  (A Gen3 failure will go back to Gen1, it doesn't go to a Gen2 intermediary).  PLX (PEX parts) had some errata with Gen3 training that require adjustments on their side.  I don't have the exact Errata titles, but there was one regarding parity in Gen3 packets and one that was regarding the PLX using only Gen3 coefficients and ignoring the "Use Preset" bit, both of which have caused some interop challenges.  Please check through the errata for your specific part carefully and apply all recommend updates.

 

 I would highly recommend setting the Xilinx IP, Advanced Mode, GT Settings tab to do Auto RX Equalization.  That will help with one of the two above. 


If that doesn't help, then you can insert a JTAG debugger as described in PG195 and capture the data.  If you provide the LTSSM .dat file produced, we can see what phase training is failing at for Gen3.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Adventurer
Adventurer
220 Views
Registered: ‎11-24-2017

Re: ZCU 106 PCIe link speed

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Thank you for sharing that info with us, @bethe,

 

Let's see what we can find within errata of PEX part.

 

Sincerely,

Bojan.

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