03-01-2019 12:26 AM
We are stuck with Male PCIE Header on ZCU106 board. We understand that it acts as an Endpoint. My question is - Is there any way we can configure it as a root port?
We want to finally connect an SSD to it(this male header through maybe some connector/adaptor) and we cannot use the FMC port 0 because we may be using it for connecting another FPGA board.
Thanks and Regards
03-01-2019 12:49 AM
you can google 'pcie female to female' and something like this may work.
Can the SSD clock by itself or requires external clocking?
03-01-2019 01:08 AM
Let's say I use the connector shared by you, if we want to connect a HHHL SSD Gen3x4, can the FPGA provide both power and clock to this?
By the way, my earlier question - Can this port be connected as Root or Bridge Port?
Thanks again !!
03-01-2019 01:33 AM
I'm afraid the connector only provides data connection. For power and clock, you need to find other ways.
from FPGA side, the pcie port can be configured to either EP or RP.
03-01-2019 02:36 AM
Thanks again. Is there any example design which can come close to what we are discussing here?
It will be great if I can get some reference to fall back upon.
03-03-2019 11:08 PM
I think you can custemize the pcie (either Intergrated Block or AXI Bridge for PCIe) to Root Port mode in Vivado.
A .xci file will be generated.
Then you can right click on the xci file and select Open IP Example Design.
You will have an root port example design.