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Contributor
Contributor
1,064 Views
Registered: ‎06-24-2011

ZCU106 as PCIe endpoint not recognized by host PC

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I have followed three (3) Xilinx video tutorials:

- PCIe with integrated block example design

- PCIe with AXI+MIG example design

- PCIe with DMA+MIG example design

 

1)  I am using ZCU106 as platform.

2)  Implementation through bitstream programming all successful in each tutorial.

3)  Configured for Gen2, X4.

4)  ZCU106 powered externally, and plugged into PCIe slot of host PC.

5)  Dip switches and jumpers of ZCU106 all correct as far as I can tell.

6)  Re-booted host PC (with ZCU106 always ON).

7)  Host PC never recognizes ZCU106.

 

(My experience with tutorial for ML605 worked perfectly, and yes, ML605 recognized by host PC; I used this as baseline to make sure I am not going krazy.)

 

What am I doing wrong with ZCU106?

Thank you.

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1 Solution

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Contributor
Contributor
759 Views
Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Update for 09/24/18, 10 am:

 

Design 2 (PCIe=>AXI=>MIG) is now working; host PC now sees zcu106.

Design 3 (PCIe=>DMA=>MIG) is now working; host PC now sees zcu106.

 

Solution => Upgrade to Vivado 2018.2 did the trick.

 

(Reminder:  Always shutdown PC, then re-boot PC [don't just re-start PC] for BIOS to recognize device on PCIe port.)

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Xilinx Employee
Xilinx Employee
1,003 Views
Registered: ‎08-02-2007

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Have you checked the first tabCapture.PNG, if the Lane width is selected ?

this will fix the GT location to the targart board correctly

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Contributor
Contributor
991 Views
Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Thank you for replying.

 

Yes, I have re-confirmed lane width has been selected as X4 (and Gen2) for all three (3) of my design experiments:

- using IP catalog to generate PCIe integrated block (design 1)

- using IPI to generate AXI+MIG (design 2)

- using IPI to generate DMA+MIG (design 3)

 

Furthermore, using eval board ML605 (pre-Vivado days) as sanity check and reference model, I have "mirrored" design 1 on ZCU106 to what was done on ML605; still, host PC does not recognize ZCU106.

 

Furthermore, I have jumped pins 3&4 on J162 to explicitly imply "PCIe PRESENT, X4"; still, host PC does not recognize ZCU106.

 

I have run out of options; hence, this forum is my last resort.

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Moderator
Moderator
987 Views
Registered: ‎02-16-2010

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Can you enable JTAG debugger option with your design in ZCU106? It can help to know the status of the LTSSM.

AR#68134 helps with the steps to test the design with JTAG debugger feature.
https://www.xilinx.com/support/answers/68134.html
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Contributor
Contributor
959 Views
Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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After taking your advice and applying it to "design 1" (the simplest one), the JTAG debugger came up with three (3) pictures, which are attached.

 

I'm no expert on the matter, but they don't look "ideal".  Any comments, suggestions, and/or advice?  Thanks!

draw_ltssm.png
draw_reset.png
draw_rxdet.png
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Contributor
Contributor
939 Views
Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Update for 09/12/18:

 

Design 1 has been solved.  I re-optimized the IP by changing the reference frequency from 250 MHz to 100 MHz.  That is the only change.

 

ZCU106 (programmed with Design 1) is now recognized by host PC, can now do reads/writes into BRAM from host PC.

 

I am proceeding to Design 2.  Thanks.

Moderator
Moderator
937 Views
Registered: ‎02-16-2010

回复: ZCU106 as PCIe endpoint not recognized by host PC

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The JTAG debugger results and the change that solved the issue seems related.

The reset state machine shows the FSM is stuck and waiting for PLL lock. This is the reason LTSSM is stuck in detect state and waiting for the GT initialization to finish.

Do you know if the host machine was sending 100MHz clock? If this was the case, configuring the IP to 250MHz might have caused the PLL lock failure.
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Contributor
Contributor
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Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Thanks for the input...

 

I don't know if the host PC was sending 100 MHz; I don't even know how to find that out.

 

What's interesting is this:

- ML605 board --> reference clock frequency was 250 MHz, host PC saw ML605.

- ZCU106 board --> reference clock frequency had to be changed to 100 MHz to make host PC see ZCU106.

 

In the meantime, I will continue to debug design 2 (AXI+MIG)...

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Contributor
Contributor
820 Views
Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Update for 09/20/18:

 

After re-visiting design 1 for clues on how to solve designs 2 & 3, I learned there is a difference between re-starting host PC vs. complete shutdown of host PC.

 

Case A Sequence of events for design 1:

- program fpga with bitstream

- zcu106 powered externally, always ON

- close vivado

- re-start host PC

- host PC up, it does NOT see zcu106

 

Case B Sequence of events for design 1:

- program fpga with bitstream

- zcu106 powered externally, always ON

- close vivado

- shutdown host PC, push power-on button on host PC

- host PC up, it sees zcu106!

 

Interesting, isn't it?

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Contributor
Contributor
760 Views
Registered: ‎06-24-2011

回复: ZCU106 as PCIe endpoint not recognized by host PC

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Update for 09/24/18, 10 am:

 

Design 2 (PCIe=>AXI=>MIG) is now working; host PC now sees zcu106.

Design 3 (PCIe=>DMA=>MIG) is now working; host PC now sees zcu106.

 

Solution => Upgrade to Vivado 2018.2 did the trick.

 

(Reminder:  Always shutdown PC, then re-boot PC [don't just re-start PC] for BIOS to recognize device on PCIe port.)

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