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[help]Problem with BMD Simulation

Visitor
Posts: 2
Registered: ‎06-08-2009

[help]Problem with BMD Simulation

[ Edited ]

I meet a problem when I simulate the DMA free_ware.

Here is the excerpt of the Modelsim log showing the errors at elaboration time :

 

do simulate_mti.do

# ** Warning: (vlib-34) Library already exists at "work".
# Reading D:\modeltech_6.4d\win32/../modelsim.ini
# "work" maps to directory work. (Default mapping)
# Model Technology ModelSim SE vlog 6.4d Compiler 2009.03 Mar 16 2009
# -- Compiling module boardx04
# -- Compiling module sys_clk_gen
# -- Compiling module sys_clk_gen_ds
# -- Compiling module BMD
# -- Compiling module BMD_64_RX_ENGINE
# -- Compiling module BMD_64_TX_ENGINE
# -- Compiling module BMD_EP_MEM_ACCESS
# -- Compiling module BMD_EP_MEM
# -- Compiling module BMD_EP
# -- Compiling module BMD_INTR_CTRL
# -- Compiling module BMD_TO_CTRL
# -- Compiling module xilinx_pci_exp_4_lane_ep
# -- Compiling module endpoint_blk_plus_v1_5
# -- Compiling module glbl
# -- Compiling module pci_exp_64b_app
# -- Compiling module xilinx_pci_exp_4_lane_downstream_port
# -- Compiling module xilinx_pci_exp_4_lane_dsport
# -- Compiling module dsport_cfg
# -- Compiling module pci_exp_usrapp_rx
# -- Compiling module pci_exp_usrapp_tx
# -- Compiling module pci_exp_usrapp_com
# -- Compiling module pci_exp_usrapp_cfg
# -- Compiling module pci_exp_4_lane_64b_dsport
# -- Scanning library directory 'D:\Xilinx\10.1\ISE/verilog/src/simprims'
# -- Scanning library directory 'D:\Xilinx\10.1\ISE/verilog/src/unisims'
# -- Compiling module IBUFDS
# -- Compiling module IBUF
# -- Compiling module VCC
# -- Compiling module GND
# -- Compiling module INV
# -- Compiling module LUT5
# -- Compiling module LUT3
# -- Compiling module LUT4
# -- Compiling module FDR
# -- Compiling module LUT2
# -- Compiling module LUT6
# -- Compiling module FDC
# -- Compiling module FDCE
# -- Compiling module FDP
# -- Compiling module BUFG
# -- Compiling module PLL_ADV
# -- Compiling module PCIE_INTERNAL_1_1
# -- Compiling module RAMB36_EXP
# -- Compiling module RAMB36SDP_EXP
# -- Compiling module FDRE
# -- Compiling module GTP_DUAL
# -- Compiling module LDP_1
# -- Compiling module FD
# -- Compiling module FDE
# -- Compiling module SRLC16E
# -- Compiling module MUXF7
# -- Compiling module FDRS
# -- Compiling module LUT1
# -- Compiling module FDRSE
# -- Compiling module FDS
# -- Compiling module FDSE
# -- Compiling module MUXCY
# -- Compiling module XORCY
# -- Compiling module RAM32X1D
# -- Compiling module GT11CLK_MGT
# -- Compiling module OBUF
# -- Compiling module LUT4_L
# -- Compiling module LUT1_L
# -- Compiling module LUT2_L
# -- Compiling module LUT3_L
# -- Compiling module MUXF5
# -- Compiling module FDPE
# -- Compiling module BUF
# -- Compiling module DCM_ADV
# -- Compiling module dcm_adv_clock_divide_by_2
# -- Compiling module dcm_adv_maximum_period_check
# -- Compiling module dcm_adv_clock_lost
# -- Compiling module BUFGMUX_VIRTEX4
# -- Compiling module MUXCY_L
# -- Compiling module SRLC16
# -- Compiling module SRL16
# -- Compiling module GT11
# -- Compiling module RAM16X1D
# -- Compiling module SRL16E
# -- Compiling module RAMB16_S18_S18
# -- Compiling module MULT_AND
# -- Compiling module MUXF6
# -- Compiling module ARAMB36_INTERNAL
# -- Compiling module BUFGCTRL
# -- Scanning library directory 'D:\Xilinx\10.1\ISE/smartmodel/nt/wrappers/mtiverilog'
# -- Compiling module PCIE_INTERNAL_1_1_SWIFT
# -- Compiling module GTP_DUAL_FAST
# -- Compiling module GTP_DUAL_SWIFT
# -- Compiling module GT11_SWIFT
# -- Compiling module PCIE_INTERNAL_1_1_SWIFT_BIT
# -- Compiling module GTP_DUAL_FAST_BIT
# -- Compiling module GTP_DUAL_SWIFT_BIT
# -- Compiling module GT11_SWIFT_BIT
#
# Top level modules:
#  boardx04
#  glbl
# vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L work work.boardx04 glbl
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading D:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll
# Loading work.boardx04(fast)
# Loading work.xilinx_pci_exp_4_lane_ep(fast)
# Loading work.IBUFDS(fast)
# Loading work.IBUF(fast)
# Loading work.pci_exp_64b_app(fast)
# Loading work.BMD(fast)
# Loading work.BMD_EP(fast)
# Loading work.BMD_EP_MEM_ACCESS(fast)
# Loading work.BMD_EP_MEM(fast)
# Loading work.BMD_64_RX_ENGINE(fast)
# Loading work.BMD_64_TX_ENGINE(fast)
# Loading work.BMD_INTR_CTRL(fast)
# Loading work.BMD_TO_CTRL(fast)
# Loading work.endpoint_blk_plus_v1_5(fast)
# Loading work.VCC(fast)
# Loading work.GND(fast)
# Loading work.INV(fast)
# Loading work.LUT5(fast)
# Loading work.LUT3(fast)
# Loading work.LUT4(fast)
# Loading work.FDR(fast)
# Loading work.LUT2(fast)
# Loading work.LUT6(fast)
# Loading work.LUT2(fast__1)
# Loading work.LUT2(fast__2)
# Loading work.LUT2(fast__3)
# Loading work.LUT2(fast__4)
# Loading work.FDC(fast)
# Loading work.FDCE(fast)
# Loading work.FDP(fast)
# Loading work.BUFG(fast)
# Loading work.PLL_ADV(fast)
# Loading work.PCIE_INTERNAL_1_1(fast)
# Loading work.PCIE_INTERNAL_1_1_SWIFT(fast)
# Loading work.PCIE_INTERNAL_1_1_SWIFT_BIT(fast)
# Loading work.RAMB36_EXP(fast)
# Loading work.ARAMB36_INTERNAL(fast)
# Loading work.RAMB36SDP_EXP(fast)
# Loading work.ARAMB36_INTERNAL(fast__1)
# Loading work.FDRE(fast)
# Loading work.GTP_DUAL(fast)
# Loading work.GTP_DUAL_FAST(fast)
# Loading work.GTP_DUAL_FAST_BIT(fast)
# Loading work.GTP_DUAL(fast__1)
# Loading work.LDP_1(fast)
# Loading work.FD(fast)
# Loading work.FD(fast__1)
# Loading work.FDE(fast)
# Loading work.SRLC16E(fast)
# Loading work.MUXF7(fast)
# Loading work.RAMB36SDP_EXP(fast__1)
# Loading work.ARAMB36_INTERNAL(fast__2)
# Loading work.LUT2(fast__5)
# Loading work.LUT2(fast__6)
# Loading work.FDRS(fast)
# Loading work.LUT1(fast)
# Loading work.FDRSE(fast)
# Loading work.FDS(fast)
# Loading work.LUT2(fast__7)
# Loading work.FDSE(fast)
# Loading work.FDRSE(fast__1)
# Loading work.FDE(fast__1)
# Loading work.MUXCY(fast)
# Loading work.XORCY(fast)
# Loading work.FDSE(fast__1)
# Loading work.RAM32X1D(fast)
# Loading work.xilinx_pci_exp_4_lane_downstream_port(fast)
# Loading work.xilinx_pci_exp_4_lane_dsport(fast)
# Loading work.GT11CLK_MGT(fast)
# Loading work.OBUF(fast)
# Loading work.pci_exp_4_lane_64b_dsport(fast)
# Loading work.LUT1(fast__1)
# Loading work.LUT2(fast__8)
# Loading work.LUT4_L(fast)
# Loading work.LUT1_L(fast)
# Loading work.LUT2_L(fast)
# Loading work.LUT2_L(fast__1)
# Loading work.LUT2_L(fast__2)
# Loading work.LUT3_L(fast)
# Loading work.LUT2(fast__9)
# Loading work.MUXF5(fast)
# Loading work.LUT2_L(fast__3)
# Loading work.LUT2_L(fast__4)
# Loading work.LUT2_L(fast__5)
# Loading work.FDPE(fast)
# Loading work.BUF(fast)
# Loading work.DCM_ADV(fast)
# Loading work.dcm_adv_clock_divide_by_2(fast)
# Loading work.dcm_adv_maximum_period_check(fast)
# Loading work.dcm_adv_maximum_period_check(fast__1)
# Loading work.dcm_adv_clock_lost(fast)
# Loading work.BUFGMUX_VIRTEX4(fast)
# Loading work.BUFGCTRL(fast)
# Loading work.MUXCY_L(fast)
# Loading work.LUT2_L(fast__6)
# Loading work.SRLC16(fast)
# Loading work.SRL16(fast)
# Loading work.LUT1_L(fast__1)
# Loading work.GT11(fast)
# Loading work.GT11_SWIFT(fast)
# Loading work.GT11_SWIFT_BIT(fast)
# Loading work.GT11(fast__1)
# Loading work.GT11(fast__2)
# Loading work.LUT2_L(fast__7)
# Loading work.RAM16X1D(fast)
# Loading work.LUT2_L(fast__8)
# Loading work.LUT2_L(fast__9)
# Loading work.SRL16E(fast)
# Loading work.RAMB16_S18_S18(fast)
# Loading work.MULT_AND(fast)
# Loading work.MUXF6(fast)
# Loading work.dsport_cfg(fast)
# Loading work.pci_exp_usrapp_rx(fast)
# Loading work.pci_exp_usrapp_tx(fast)
# Loading work.pci_exp_usrapp_cfg(fast)
# Loading work.pci_exp_usrapp_com(fast)
# Loading work.sys_clk_gen_ds(fast)
# Loading work.sys_clk_gen(fast)
# Loading work.sys_clk_gen_ds(fast__1)
# Loading work.sys_clk_gen(fast__1)
# Loading work.glbl(fast)
# ** Warning: (vsim-PLI-3003) ../board.v(123): [TOFD] - System task or function '$fsdbDumpfile' is not defined.
#         Region: /boardx04
# ** Warning: (vsim-PLI-3003) ../board.v(124): [TOFD] - System task or function '$fsdbDumpvars' is not defined.
#         Region: /boardx04
# ** Warning: (vsim-3015) D:/Xilinx/10.1/ISE/verilog/src/unisims/GTP_DUAL.v(3488): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
#         Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i /genblk1/gtp_dual_fast_1
# ** Warning: (vsim-3015) D:/Xilinx/10.1/ISE/verilog/src/unisims/GTP_DUAL.v(3488): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.
#         Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i /genblk1/gtp_dual_fast_1
# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.
#         Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport
#       Runtime, LMTV v12.4
#       Copyright (c) 1984-2009 Synopsys Inc. ALL RIGHTS RESERVED
#       You can use the Browser tool to configure the SmartModel
#       Library and access information about SmartModels:
#          $LMC_HOME/bin/sl_browser
#
#       SmartModel product documentation is available here:
#          $LMC_HOME/doc/smartmodel/manuals/intro.pdf
#          http://www.synopsys.com/products/lm/doc/smartmodel.html
#
# (LMTV) (3006)Error: Model named 'PCIE_INTERNAL_1_1_SWIFT' was not installed at $LMC_HOME/models/PCIE_INTERNAL_1_1_SWIFT for this platform -
#                      $lm_model failed to find model. Verify that instance path is correct.
# (LMTV) (3006)Error: Model named 'GTP_DUAL_FAST' was not installed at $LMC_HOME/models/GTP_DUAL_FAST for this platform -
#                      $lm_model failed to find model. Verify that instance path is correct.
# (LMTV) (3006)Error: Model named 'GTP_DUAL_FAST' was not installed at $LMC_HOME/models/GTP_DUAL_FAST for this platform -
#                      $lm_model failed to find model. Verify that instance path is correct.
#       Model gt11_swift: Model Vendor: xilinx'.
# Running test {sample_smoke_test0}......
# [                   0] : System Reset Asserted...
# [             4995000] : System Reset De-asserted...
# [             8522100] : Transaction Reset Is De-asserted...
# Break key hit

 

I have changed the file modelsim.ini and comipled the library with the following command:

compxlib -s mti_se -arch all -lib all -l verilog -w

but 'PCIE_INTERNAL_1_1_SWIFT' and 'GTP_DUAL_FAST' are not appear in the model list, and some models are lost too. WHY?

 

How to correct the errors? Please help!

Message Edited by hithust on 06-08-2009 08:51 PM
Message Edited by hithust on 06-09-2009 12:34 AM
Message Edited by hithust on 06-09-2009 01:39 AM
Newbie
Posts: 1
Registered: ‎01-10-2010

Re: [help]Problem with BMD Simulation

The Xilinx has two  design solution for PCI express  demo...

 

1)   DMA ( 895 )

2)   BMD (1025)

 

There is simulation env for DMA design . no simulation for  BMD(1052) design.

 

The DMA works fine.  You are having issue with MODELSIM VERSION   use 6.5+ MODELSIM TOOLS.This design works properly.

 

There are two ways to simuate PCI end bus interface,   i)  SWIFT  ii)  SECURE IP, They secure ip is easy to use,

compile lib from ISE and link to MODELSIM 6.5+.

 

 

thanks

 

 

 

Xilinx Employee
Xilinx Employee
Posts: 202
Registered: ‎08-02-2007

Re: [help]Problem with BMD Simulation

using seccureip is simple and easier.

Howevver if you need to use smartmode, please run

%xilinx%\ISE\smartmodel\nt\installed_nt\bin\sl_admin.exe to install smartmodel

 

Xilinx Employee
Posts: 615
Registered: ‎04-06-2010

Re: [help]Problem with BMD Simulation

I don't believe that Modelsim supports SmartModels in 6.4.  

 

When you use secureip, make sure to add the reference to the library in your vsim command:

 

 vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L secureip -L work work.boardx04 glbl