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Contributor
Contributor
195 Views
Registered: ‎05-22-2018

length matching for PCIe data lanes

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Dear All,

I am designing a custom PCIe 3 gen x4 add on board with xczu21dr. Is length matching required among the four data lanes (for both tx & rx)?

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Xilinx Employee
Xilinx Employee
158 Views
Registered: ‎08-02-2007

回复: length matching for PCIe data lanes

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Are  you talking about the the skew between lanes ?

The GTH inside the FPGA is capabable of deskew the differences of the lanes 

However you still need to follow the spec for the skews requirement 

the Allowable Interconnect Lane-to-Lane Skew is 1.6ns including add in card 0.35ns and 1.25ns n system board in Gen2

 Please find more detailed info in the spec 

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Xilinx Employee
Xilinx Employee
168 Views
Registered: ‎07-26-2012

Re: length matching for PCIe data lanes

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Although I'm not sure if my undestand your questions correctly, a PCIe packet is distributed byte by byte in each lane of PCIE ( Bypte Striping).

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Xilinx Employee
Xilinx Employee
159 Views
Registered: ‎08-02-2007

回复: length matching for PCIe data lanes

Jump to solution

Are  you talking about the the skew between lanes ?

The GTH inside the FPGA is capabable of deskew the differences of the lanes 

However you still need to follow the spec for the skews requirement 

the Allowable Interconnect Lane-to-Lane Skew is 1.6ns including add in card 0.35ns and 1.25ns n system board in Gen2

 Please find more detailed info in the spec 

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Don't forget to reply, give kudo and accept as solution
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Contributor
Contributor
149 Views
Registered: ‎05-22-2018

回复: length matching for PCIe data lanes

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Thanks for the information. I am now able to check this in lane-to-lane skew section of specifications.

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