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Explorer
Explorer
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Registered: ‎05-14-2017

pcie integrated block kintex7 (pg054) vs ultrascale (pg156)

I'm porting a pcie design from kintex7 to ultascale kintex and noticed that in the ultrascale pcie v4.4 it has a four AXI bus.

My original design uses the pcie v3.3 and only has two axi bus, they are the m_axis and a s_axis. I believed Both side can initiate r/w traffic.

But the pcie v4.4 has 4 axi bus, not familiar why there are 4 axi bus, since i was able to do it with two.

If I want to use the original 2 axi bus from my pcie v3.3 design which is the master(m_axis_...)  and slave (s_axis_...) then should I use the pcie v4.4 of (m_axis_cq...) and (s_axis_cc) and leave the other two (s_axis_rq) and (m_axis_rc) open?

 

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Moderator
Moderator
67 Views
Registered: ‎02-11-2014

Re: pcie integrated block kintex7 (pg054) vs ultrascale (pg156)

Hello @tchin123,

Please refer to your original post on this topic: https://forums.xilinx.com/t5/PCI-Express/PCIe-v3-3-Kintex-to-PCIe-v4-4-Ultracscale-conversion/m-p/933175#M12995

Thanks,
Cory

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