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Contributor
Contributor
8,444 Views
Registered: ‎09-07-2014

pcie link width degradation

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Hi.

I generate pcie gen2 5G x2 ep core using core generator for virtex7. I simulate the design in modelsim 10.2 with the example design, but I noticed the link width at start is x8 than became x2 (as requested) but after that changed to x1.

The pcie fabric signals (tx and rx) change appropriately with the signal pl_sel_lnk_width.

The last degradation occurs before trn_reset deasserted.

Why is that? What can be done to establish x2 simulation?
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Contributor
Contributor
15,689 Views
Registered: ‎09-07-2014

Re: pcie link width degradation

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So, now I found my problem is a known one - AR61652.

 

The solution is to upgarde modelsim version to 10.3, or using other simulaton tool.

 

FYI.

 

 

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Xilinx Employee
Xilinx Employee
8,433 Views
Registered: ‎07-11-2011

Re: pcie link width degradation

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Hi,

 

You can use atatched pdf to below Xilinx AR to debug the casue for link width train down which can give you a clue on what can be done to achieve X2 link

http://www.xilinx.com/support/answers/56616.html

 

 

Hope this helps

 

-Vanitha

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Contributor
Contributor
8,416 Views
Registered: ‎09-07-2014

Re: pcie link width degradation

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Hi Vanitha,

 

I decided to change my simulation tool - instead Modelsim10.2 I use ISim. 

I create new project with ISE (gather all example design files) and initiate behavioral simalution via ISim.

 

Took some time but now the link width and rate are as I expected (i.e. pcie_ep_x2_gen2).

So, for now I know my source files are good enough.

 

The problem is this pcie_ep should serviced other design modules, which should be re-simulate each time, and ISim speed is very slow compare to Modelsim.

 

What can be done in order to solve Modelsim behavior? The source files are the exactly same.

 

ThanX.

 

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Contributor
Contributor
15,690 Views
Registered: ‎09-07-2014

Re: pcie link width degradation

Jump to solution

 

So, now I found my problem is a known one - AR61652.

 

The solution is to upgarde modelsim version to 10.3, or using other simulaton tool.

 

FYI.

 

 

0 Kudos