01-18-2019 07:26 AM
The PCIe v3.3 for the 7 series integrated block has 2 AXI bus. One is call m-axi and the other s-axi bus
I'm aware that the m-axi bus can issue read and write request. Is the s-axi bus limited to transmitting completion packet only. My application only support request from the root complex therefore on the FPGA side of the s-axi interface I never issue any request.
But, Can the s-axi bus also issue read and write request?
Since the TLP has the FMT and TYPE field which actually define the read and write packet, I believed it is the Pcie/TLP protocol that should define the request and not the m-axi and s-axi bus. Is this correct.
This question came up because when I try to port my design to a UltraScale Kintex device I noticed the Integrated Block PCIe v4.4 now has 4-axi bus instead of the 2-axi bus that v3.3 has.Why is there four, I'm a little perplexed?
01-24-2019 06:29 PM
For PG054， the s_axi are the tx side that is to recieve the request from the user and send to the other PCIE device and you can issue read and write from user
M_axi side is the RX as the protical mentioned and it receives from the link partiner to recieved read /write commend or the completions
the format is like the spec
for PG213 (ultrascale plus) 4 interfaces are the request received from the link and the user /the completion recieved from the user and link are seperated
the format is not the same as the Spec
01-25-2019 06:47 AM
I do not follow your answer, it is not very clear and very confusing. Can someone else answer this
In reference to PG054 there are two bus M_AXIS and S_AXIS.
The M_AXIS is the master which represent the Root Complex side and it issue read and write request.
My question is can the S_AXIS which I believed to represent the Slave bus, can also issue read and write request. ...or is it limited to returning Completion packt only
Since there is only two bus as describe in PG054, I would assume the Slave bus (S_AXIS) should be able to .issue read and write request but I'm not sure