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Observer bmoore
Observer
323 Views
Registered: ‎01-09-2018

reference PL PCIe root port design

I am interested in obtaining the reference design featured in the following Xilinx Wiki link:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842034/ZynqMP+Linux+PL+PCIe+Root+Port

Can anyone help? thanks

 

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Moderator
Moderator
224 Views
Registered: ‎02-16-2010

Re: reference PL PCIe root port design

@bmoore

Through EZmove, I have sent you an example for the PL PCIe Root port design. It is created with 2018.1 Vivado version. It has .tcl script that can be sourced in Vivado to create the design automatically. Please refer to the design creation document for the guidance for steps involved with IPI design and Petalinux build process.

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