We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Participant ultragreen
Registered: ‎09-08-2016

setting 2 GB for axi_pci_bridge



My design is :


 AXI_pci_bridge <-> AXI_interconnect <-> 4 GB DDR4 ( MIG with AXI interface )

the board containing 4Gb DDR4 memory is connected to host PC through PCIe.


When I configure PCIe:BARs of  AXI_PCIE_BRIDGE and set the size  as 512Mb or 1GB for memory Type. the system works fine.

but as soon as I increases the size to 2 Gb / 4Gb the PC does not boots up and gets stuck .


I am using Vivado 2016.2 , virtx ultrascale FPGA.

Please help me figure out the problem

0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎11-25-2015

Re: setting 2 GB for axi_pci_bridge

Hi @ultragreen,



So the issue here seems to be your AXI BAR is too large


So in the AXI BARS tab, check your AXI Base Address and AXI High Address between the two design


For Example, Suppose if your are setting the translation to 0x5730_0000, that means it's using up the upper 12 bits


Therefore the maximum BAR size you can have is 20 bit.


In PG194 there's an address translation example and how it works starting at page 43


If you look at Figure 3-4: AXI to PCIe Address Translation then it kinda explain how it mask the addresses and stuff. 





Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.


0 Kudos
Scholar markcurry
Registered: ‎09-16-2009

Re: setting 2 GB for axi_pci_bridge



As @ultragreen mentioned, 512MB, and 1GB work fine so his BARs of 29, and 30 bits work fine.  So I'm not sure where you're coming up with that 20 bit limitation.


Anyway - the root cause of the issue is NOT the FPGA - it's the BIOS/OS on the PC.  We've found for our PC configurations anything bigger than 256MB (28 bit BARs) would cause the PC to refuse to boot.  For some ARM processors, this goes down to 128MB BARs.


Note that I've little insight into the (blackbox) BIOS.  Linux is open source, so there may be room to dig there - but for us, we've just learned to live with a limitation of 27, or 28 bits for the PCIE BARs.





0 Kudos
Xilinx Employee
Xilinx Employee
Registered: ‎11-25-2015

Re: setting 2 GB for axi_pci_bridge

Hi @markcurry,


I just gave an example for him so that he can correlate BAR size and Address transalation Value..


Your PC configuration limitation makes sense too




0 Kudos