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an_coco
Visitor
Visitor
221 Views
Registered: ‎12-18-2018

请求帮助。我是用的zu7eg 编译pcie tandem 模式是遇到错误。!!

我是用的器件zu7eg-21156i  在编译tandem 模式的时候,修改约束文件,就会出现下面的error  这个是什么问题?  请求帮助。

 

 

[Constraints 18-4610] Tandem stage 1 cell 'refclk_ibuf' has the property HD.TANDEM_IP_PBLOCK set to 'Stage1_Main'. It also has a conflicting LOC constraint set to 'GTHE4_COMMON_X0Y4'. This site is outside of pblock 'pcie4_uscale_plus_0_i_inst_pcie4_uscale_plus_0_Stage1_main'. Please resolve this conflict by removing the LOC constraint or changing the value of HD.TANDEM_IP_PBLOCK to a pblock that contains the site.

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nmanitri
Xilinx Employee
Xilinx Employee
140 Views
Registered: ‎06-13-2018

Hi @an_coco 

You need to resize the pblock. 'GTHE4_COMMON_X0Y4' this site si outside the pblock. Please create an IP example design(you can refer the below video link) and put the correct constraint to resize the Pblock.

https://www.xilinx.com/video/hardware/create-tandem-pcie-design-for-kcu105.html

Regards,

Naveen

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