2% duty cycle in XDMA performance testing

[tristan.qiu]

I am trying to follow a very similar design as instructed in https://www.xilinx.com/video/technology/dma-for-pci-express.html with AR65444 sw toolkit.

Card is recognized, run_test passed, everything looks okay. Except that performance_hwcount script only gives me 2% duty cycle compared with 87% achieved in https://www.xilinx.com/video/technology/getting-the-best-performance-with-dma-for-pci-express.html . Strangely, it prints the data rate only as *****. However, I can compute it as: 5G*4*2%/8=50MBps!

I used lspci command to check the link status:

x4 lines, Gen 1 speed, MPS 256B, MRRS 512B, also changed the transfer size to 32K in the performance_hwcount.

The IP has 2 channels for C2H and H2C, respectively.

Linux OS is Ubuntu 14.04; board is ZC706; Vivado is 2017.4 and XDMA IP version is 70325 (patch for 2017.4)

The configuration is not that high but it looks okay, right?

2% is too low !!!

Is there anyone can help me?

[liy]

is it C2H or H2C， maybe you can insert ILA to check if any signal （ready、valid for example ） is not asserted as expected

[tristan.qiu]

It is C2H.

As for H2C, it shows:

data transferred = 0 bytes

perf.clock_cycle_count=0

perf.data_cycle_count=0

?!?!!!!!!

How come?!

[liy · Accepted solution]

please try to use axi interconnect instead of smartconnct

try to change the offset of axi address