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Visitor suisui0207
Visitor
724 Views
Registered: ‎01-09-2019

2000t axi memory mapped to pcie IP issue

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I generated one axi memory mapped to pcie IP, and open example design,I found s_* ports are not used for this example,so I connect a AXI master model to s_* for Upstream requeset. When simulate one issue occur:Upstream read requeset get a S_AXI_RRESP=2'b10 status. From wave file I found “/board/XILINX_AXIPCIE_EP/axi_pcie_0_i/inst/comp_axi_enhanced_pcie/m_axis_rc_tdata[127:0]=128'b 7417d986 01a00000 00002004 0a000000" the completion is Unsupported Request (UR).Why have this issue? Please help me solve the issue. Thank you!
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1 Solution

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Xilinx Employee
Xilinx Employee
591 Views
Registered: ‎07-26-2012

Re: 2000t axi memory mapped to pcie IP issue

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The root port model generated with this IP does not return a completion to a Memory Read request from EP. TSK_TX_CoMPLETION_DATA can be used when you modify the RP code in order to return a completion.

 

The following is just a simple example  :

<< pci_exp_usrapp_com.v >>

// Add the following in TSK_3DW

 reg [7:0]  B1;
 reg [15:0] B23;
 
 
 reg [2:0] tc_;
 reg [9:0] len_;
 reg [11:0] byte_count_;
 reg [6:0] lower_addr_;
 reg [2:0] comp_status_;
 reg ep_;

begin

// Omitted

    `PCI_EXP_MEM_READ32: begin
     if ( txrx == 0) begin  
          // For Completion
      B1  =  frame_store_rx[1];
      B23 = {frame_store_rx[2], frame_store_rx[3]};     
     
      tc_   = B1[6:4];
      len_ = B23[9:0];
     
      byte_count_  = (len_ * 4);
      lower_addr_  = 7'h00;
      comp_status_ = 3'b000;
      ep_           = 1'b0;
     
      requester_id =  {frame_store_rx[4], frame_store_rx[5]};
      tag =  frame_store_rx[6];

      
      board.RP.tx_usrapp.TSK_TX_COMPLETION_DATA(tag, tc_, len_, byte_count_, lower_addr_, comp_status_, ep_);
     
      end
    end

cmplD.png
8 Replies
Xilinx Employee
Xilinx Employee
643 Views
Registered: ‎07-26-2012

Re: 2000t axi memory mapped to pcie IP issue

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What kind of request did you make? Can you let me know the content of the request and also IP version because I will try to reproduce it?

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Visitor suisui0207
Visitor
623 Views
Registered: ‎01-09-2019

Re: 2000t axi memory mapped to pcie IP issue

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IP version="2.9",requeset is Memory read,all memory read is the same situation

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Xilinx Employee
Xilinx Employee
592 Views
Registered: ‎07-26-2012

Re: 2000t axi memory mapped to pcie IP issue

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The root port model generated with this IP does not return a completion to a Memory Read request from EP. TSK_TX_CoMPLETION_DATA can be used when you modify the RP code in order to return a completion.

 

The following is just a simple example  :

<< pci_exp_usrapp_com.v >>

// Add the following in TSK_3DW

 reg [7:0]  B1;
 reg [15:0] B23;
 
 
 reg [2:0] tc_;
 reg [9:0] len_;
 reg [11:0] byte_count_;
 reg [6:0] lower_addr_;
 reg [2:0] comp_status_;
 reg ep_;

begin

// Omitted

    `PCI_EXP_MEM_READ32: begin
     if ( txrx == 0) begin  
          // For Completion
      B1  =  frame_store_rx[1];
      B23 = {frame_store_rx[2], frame_store_rx[3]};     
     
      tc_   = B1[6:4];
      len_ = B23[9:0];
     
      byte_count_  = (len_ * 4);
      lower_addr_  = 7'h00;
      comp_status_ = 3'b000;
      ep_           = 1'b0;
     
      requester_id =  {frame_store_rx[4], frame_store_rx[5]};
      tag =  frame_store_rx[6];

      
      board.RP.tx_usrapp.TSK_TX_COMPLETION_DATA(tag, tc_, len_, byte_count_, lower_addr_, comp_status_, ep_);
     
      end
    end

cmplD.png
Visitor suisui0207
Visitor
551 Views
Registered: ‎01-09-2019

Re: 2000t axi memory mapped to pcie IP issue

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Thank you very much, and I found also need config RP's bus master enable、memory space enable、I/O space enable

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Visitor suisui0207
Visitor
385 Views
Registered: ‎01-09-2019

Re: 2000t axi memory mapped to pcie IP issue

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I use the IP on FPGA board, but host  black screen. There is a problem, Catc display as attechment: after  Host send wrie command for ip bus master 、memory spece enable、I/O space enable . IP behaviour is error . Can you help me solve this problem

error.png
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Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎07-26-2012

Re: 2000t axi memory mapped to pcie IP issue

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The following example is for Gen1 x1 but normaly setting of PCIe configuration is done like this. It is strange that the EP sends a memory write transaction to the host while the host is setting up the EP's configuration register.

It is recommended that you program the example design and check that the configuration register can be read and written correctly.

 

Config_reg_setup.png

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Visitor suisui0207
Visitor
348 Views
Registered: ‎01-09-2019

Re: 2000t axi memory mapped to pcie IP issue

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Thank you very much and I will continue work on it

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Visitor suisui0207
Visitor
325 Views
Registered: ‎01-09-2019

Re: 2000t axi memory mapped to pcie IP issue

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I have solved the strange memory write, and black screen also solved. But I am confused why memory write at this time can prevent IP send config read completion to host?

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