2013.4 to 2014.2 gives clock mismatch on AXI_MM to PCIe Core

[sunemai]

Hi!

I've searched the forum and internet for the following issue, but no luck:

A fully working design in Vivado 2013.4, with an AXI PCIe core with 1 lane configured, was auto-upgraded to 2014.2.

After upgrade, validate design gives the following two errors:

[xilinx.com:ip:axi_pcie:2.4-1] /axi_pcie_0 axi_aclk must be connected to axi_aclk_out  

[BD 41-238] Port/Pin property FREQ_HZ does not match between /axi_pcie_0/axi_ctl_aclk(125000000) and /axi_pcie_0/axi_ctl_aclk_out(62500000) 

Regarding the first error, the signals are connected, both in the original and in the upgraded design.

Regarding the second, the frequency parameters cannot be changed in the Vivado GUI - they seem to be locked.

If i configure the PCIe core for link speed 5.0 GT/s (instead of the original 2.5 GT/s), leaving everything else unchanged, the design passes both validation and implementation, except that a few timing constraints are not met - which is not surprising, given that my axi_ctl_aclk was just doubled. 

I suspect is because every PCIe configuration _except_ 1 lane x 2.5 GT/sec runs with the high clock rate. 

So, what to do, if i want to keep my 1 lane x 2.5 GT/sec?

Is there a workaround or procedure to force both clocks to 62.5 MHz that I don't know of?

Best regards

Sune

P.S.: I won't be able to provide feedback before in +12-18 hours, so I hope the above information is enough.

[kotir]

Hi ,

This might be due to the clock outputs frequency in IPI is now with 62.5Mhz for x1gen1 & 125Mhz for other configurations.

Check if you can modify the clock input accordingly.

Regards,

KR

[sunemai]

Hi, and thanks for the quick reply!

Yes, I certainly agree with your observation about the frequencies - they should both be 62.5 MHz in my configuration. But the frequencies actually associated with the ports seem to be locked and not editable (grayed out) in the GUI. 

Is there a procedure (that I am not aware of), which allows me to override the automatic IPI setting of 125 MHz on the input port?

Best regards

Sune

[kotir]

Hi ,

I believe you should be able to edit the IPI design and the configurations of IPs in it.

Can you check the IP status for the IPI design , i believe you might have done some changes which might resulted in the locking of IP's in the IPI design.

Regards,

KR

[sunemai · Accepted solution]

Ok, I think we're getting closer here:

If I start a new clean project in 2014.2, and add the axi_pcie core, the IP report contains the following key-words: 

design_1_axi_pcie_0_0 | Up-to-date | No changes required | *(1) | AXI Memory Mapped | 2.4 | 2.4 | Included | xc7k325tffg900-2 |

- and the GUI element has no axi_aclk input on the left hand side of the IP-block. 

In the upgraded design, the corresponding report_ip_status line is:

| design_1_axi_pcie_0_0         | Up-to-date | No changes required |  *(7)     | AXI Memory Mapped  | 2.4     | 2.4                   | Included   | xc7k325tffg900-2  

i.e., completely similar. But here, the GUI contains an axi_aclk input on the left (which has a locked frequency of 125 MHz, even though the corresponding output is 62.5 MHz).

Deleting the PCIe block and adding it again manually solves the problem. But auto-upgrade from 2013.4 to 2014.2, apparently has a small problem.

Best regards

Sune