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raad
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Registered: ‎05-11-2012

3DW or 4DW memory request

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Hello everybody,

 

I am wondering if I my PIO-Logic should be able to handle both 3DW and 4DW memory requests.
 In other words, how does the OS decide between using 3DW and 4DW TLPs.

 

 

Regards

- Raad

 

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barco2
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Registered: ‎02-13-2009

@raad wrote:
Why does the OS sends 3DW memory-requests to my FPGA while both (the OS and FPGA) use 64-bit addressing ?

Because even though your core offers a 64-bit BAR, the BIOS and/or operating system was able to place it in the lower 4GB of the address space during enumeration. BAR0 will have the 32bit address and BAR1 should be programmed to 0x00000000. And for accessing a 32-bit address, the PCIe spec requires usage of 32-bit Memory transfers. It is not permitted to use 64-bit addressing with the upper 32-bit set to 0, although this usually works with most PCIe implementations.

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markus.offergeld
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Registered: ‎02-28-2011

Hi,

 

The 3DW and 4DW request depend on the addressing type you use:

32 Bit addressing -> 3DW (1DW address)

64 Bit addressing -> 4DW (2DW address)

 

Regards Markus

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raad
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Registered: ‎05-11-2012
Thank you Markus !

I guess my question wasn't clear enough.

I am using a x86_64 Linux. And the pci-express core which I use in my design hast one 64-bit addressable memory-region.
The receive-engine recognizes just 3DW memory-requests.

My driver supports memory-mapping so a user space application can map its virtual-memory to device´s memory and write to it.

Now my question is:

Why does the OS sends 3DW memory-requests to my FPGA while both (the OS and FPGA) use 64-bit addressing ?
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barco2
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Registered: ‎02-13-2009

@raad wrote:
Why does the OS sends 3DW memory-requests to my FPGA while both (the OS and FPGA) use 64-bit addressing ?

Because even though your core offers a 64-bit BAR, the BIOS and/or operating system was able to place it in the lower 4GB of the address space during enumeration. BAR0 will have the 32bit address and BAR1 should be programmed to 0x00000000. And for accessing a 32-bit address, the PCIe spec requires usage of 32-bit Memory transfers. It is not permitted to use 64-bit addressing with the upper 32-bit set to 0, although this usually works with most PCIe implementations.

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raad
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Registered: ‎05-11-2012
Thank you Barco2 ! :)
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