7 Series Integrated Block for PCI Express interrupt_req line assertion during read
We have a design using the 7 Series Integrated Block for PCI Express v 3.3 configured as a gen1 x1 endpoint in a xc7a15ticpg236-1L FPGA. I'm using Vivado 2019.2.
We are getting FFFF's in read completions while running an application with interrupts. Using a logic analyzer and pulling the interrupt_req signal out to a pin I could see that the bad reads were occurring only when a read begins and the interrupt_req signal goes high in the time between the read request is on the bus and the completion TLP containing FF's 10ms later (it looks like something is timing out). It looked like the assertion of interrupt_req during a read was causing the bad completion.
To test further I changed my FW to pulse the interrupt_req signal and then did a series of back to back reads. FW with no pulsing results in no FF's, FW pulsing every 320ns resulted in numerous FF's (this was a register that should read 00's). FW pulsing the interrupt_req signal every 128us resulted in fewer bad reads, but there were still some FF's. The fact that there are fewer failed reads when interrupts are being pulsed more slowly also points to the problem being simultaneous reads and interrupts.
I tried this same test with a 50T sized Artix-7 and AXI Memory Mapped to PCI Express v2.9 IP and read millions of times with no FF's. Is there something wrong with the 7 Series Integrated Block for PCI Express IP?
This is with MSI interrupts. We have a different problem with legacy but we will address that later.