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Adventurer
Adventurer
300 Views
Registered: ‎03-06-2015

7 Series Integrated Block for PCIe in Vivado vs ISE

Hi, we are using xc7vx485tffg1157-1 (active) in our customized board.

previously in 1st version we are tested with 7 Series Integrated Block for PCIe in ISE it is worked fine.

 

presently in 2nd version, unexpectedly PCIe lines are reversed but everything was same except these lane reversal.

 

In 7 Series FPGAs Integrated Block for PCIe UG477, there is an option Lane reversal

we have selected this and tested, we are not getting any link.

 

we are also tested in vivado, using 7 Series Integrated Block for PCIe v3.1and the Lane reversal is enabled. In Vivado we got Link.

 

is there any modifications required? rather than this Lane reversal in ISE.

 

Please suggest me

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

The document is pg054.

Not all kinds of lane reversal are supported, only the reversals  like  7-0 to 0-7 are supported.

Either part of the link support lane reversal is enough, so if the link partner support it, it is not necessary to set this option for the FPGA.

For the ISE, double check  the constraint file and make sure there is no issue in the pin assignment.

You can also check pl_lane_reversal_mode signal to make sure if the reversal is working or not 

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Adventurer
Adventurer
220 Views
Registered: ‎03-06-2015

Hi,

Thanks for the reply @liy .

 

1 )Not all kinds of lane reversal are supported, only the reversals like 7-0 to 0-7 are supported.

We are using X4 lane  and lanes are reversed like 0-3 to 3-0 and i have checked in the UG477 datasheet that this kind of reversal is supported by the device.

2) Either part of the link support lane reversal is enough, so if the link partner support it, it is not necessary to set this option for the FPGA.

Virtex-7 and MPC8641 are link partners and there are direct PCIe lines  between them. MPC8641 does not have the option of lane reversal hence we are enabling lane reversal parameter at Virtex-7.

3) For the ISE, double check the constraint file and make sure there is no issue in the pin assignment.

Coming to constraints We are using the same file that is generated by the ipcore and also cross verified, we didn't find any issue . Do we need to modify it if we use lane reversal?

4) You can also check pl_lane_reversal_mode signal to make sure if the reversal is working or not 

In ISE we will check it and update you.

In Vivado Link is not consistency, we are getting the link alternately with board reset this is another issue

Vivado we have cross checked this parameter, when we got the link the value of this parameter is 2 and if there is no link it is showing 0

 

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Adventurer
Adventurer
247 Views
Registered: ‎03-06-2015

@liy 

Not all kinds of lane reversal are supported, only the reversals like 7-0 to 0-7 are supported.

We are using 0-3 to 3-0 reversal which is supported . we have gone through the UG477 datasheet.

Either part of the link support lane reversal is enough, so if the link partner support it, it is not necessary to set this option for the FPGA.

Virtex-7 and MPC8641 are link partners. Processor doesn't have support for lane reversal hence we are doing it at virtex-7.

For the ISE, double check the constraint file and make sure there is no issue in the pin assignment.

We are using the constraints file that is generated by the IP core. Do we need to change the constraint file if we use lane reverse.

You can also check pl_lane_reversal_mode signal to make sure if the reversal is working or not

we have tested this parameter pl_lane_reversal_mode in  ISE, it is constantly showing 0 but sometimes it is observed to be 2 (which means x4 lane reversed) even in that case we are unable to get link.

We are not able to understand why the parameter pl_lane_reversal_mode is 0 even though after enabling lane reversal in pcie IP core.

 

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Adventurer
Adventurer
199 Views
Registered: ‎03-06-2015

@liyplease reply me

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