02-16-2016 12:55 PM
Are there any example designs that show how to configure the 7-Series Integrated Block for PCIe with an Expansion ROM, and how to connect it to the memory (I'd like to use BRAM) where the Expansion ROM is located? I have been unable to locate one. I've used the AXI PCIe IP before, but it doesn't seem to support Expansion ROMs and the Integrated Block IP's interfaces are a little more complex.
12-20-2017 08:45 PM
Do you solve it? I have the some problem, I do not know how the BIOS copy the code of Expansion ROM to the RAM.Can you give any suggest.
08-16-2020 12:22 AM
I don't think there is an example design for this, but from looking at the documentation, but it seems like the expansion ROM is simply treated as "BAR 6". In which case, you would handle requests to read the option ROM just like requests against BAR0-BAR5, except you would route the access to your option ROM data. If the higher-level IP cores don't support the option ROM, then you may be out of luck. For Virtex 7, UltraScale, and UltraScale+, you could use the code in this repo: https://github.com/alexforencich/verilog-pcie. However, it does not currently support the 7-series PCIe endpoint, which has a very different interface.