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kaesar
Contributor
Contributor
603 Views
Registered: ‎01-09-2017

7 Series Transceivers problems

Hi, I am working on a pcie project on my ZC706 board, it used to work fine, but suddenly the core cannot be detected by the host, then I find out that the output clock of IBUFDS_GTE2 has stopped.

I have done some test on other PCs with other version of software(Vivado 2019.1/2016.4 and ISE14.7 ), the result is the same(the output clock of IBUFDS_GTE2 has stopped ), then I do the same test with another zynq board(used to work fine), the result is the same. But when replacing the FPGA with XC7A200T on another board, the device works well, so weird.

I need some help, thanks a lot.

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8 Replies
orondard
Visitor
Visitor
585 Views
Registered: ‎11-29-2018

Hi,

Does it do the same with Xilinx reference design ?
I suppose, that you let Xilinx IP drive IBUFDS_GTE2 CEB pin.
Can you probe PCIE_CLK_Q0_C_P/N to check if clock disapears from IBUFDS_GTE2 point of view ?

Olivier

kaesar
Contributor
Contributor
571 Views
Registered: ‎01-09-2017

the result is the same with Xilinx reference design.

the PCIE_CLK_Q0_C_P/N cannot be probed with ILA, but i can see the PCIE_CLK_Q0_C_P/N waveform with oscilloscope.

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orondard
Visitor
Visitor
551 Views
Registered: ‎11-29-2018

Speaking about clock waveform, note that following DS187(v1.20.1) table 86 and DS182 (v2.18) table 55, ZYNC7000 GTP requires a slightly higher clock Vidiff (350mV) than Kintex7 GTX (250mV).

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kaesar
Contributor
Contributor
511 Views
Registered: ‎01-09-2017

that is not the reason of my problem, it cannot even work with SI5324C.

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borisq
Xilinx Employee
Xilinx Employee
497 Views
Registered: ‎08-07-2007

hi @kaesar 

 

did you test this bit file or mcs file in the Ready to Download folder?

 

Thanks,

Boris

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kaesar
Contributor
Contributor
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Registered: ‎01-09-2017

Both the bit and mcs file have been testd, done is high, but pcie device cannot be detected, and the user_clk_heartbeat is always 0.   

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borisq
Xilinx Employee
Xilinx Employee
450 Views
Registered: ‎08-07-2007

hi @kaesar 

 

are all jumpers and switches connected as default?

you can refer to appendix A of the following document for the default connections.

 

https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf

 

Thanks,

Boris

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kaesar
Contributor
Contributor
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Registered: ‎01-09-2017

all jumpers and switches are connected as default.

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