10-15-2019 05:07 AM
Hi, I am working on a pcie project on my ZC706 board, it used to work fine, but suddenly the core cannot be detected by the host, then I find out that the output clock of IBUFDS_GTE2 has stopped.
I have done some test on other PCs with other version of software(Vivado 2019.1/2016.4 and ISE14.7 ), the result is the same(the output clock of IBUFDS_GTE2 has stopped ), then I do the same test with another zynq board(used to work fine), the result is the same. But when replacing the FPGA with XC7A200T on another board, the device works well, so weird.
I need some help, thanks a lot.
10-15-2019 05:40 AM
Does it do the same with Xilinx reference design ?
I suppose, that you let Xilinx IP drive IBUFDS_GTE2 CEB pin.
Can you probe PCIE_CLK_Q0_C_P/N to check if clock disapears from IBUFDS_GTE2 point of view ?
10-15-2019 06:36 AM
the result is the same with Xilinx reference design.
the PCIE_CLK_Q0_C_P/N cannot be probed with ILA, but i can see the PCIE_CLK_Q0_C_P/N waveform with oscilloscope.
10-15-2019 08:11 AM
Speaking about clock waveform, note that following DS187(v1.20.1) table 86 and DS182 (v2.18) table 55, ZYNC7000 GTP requires a slightly higher clock Vidiff (350mV) than Kintex7 GTX (250mV).
10-15-2019 11:24 PM
did you test this bit file or mcs file in the Ready to Download folder?
10-17-2019 01:52 AM
are all jumpers and switches connected as default?
you can refer to appendix A of the following document for the default connections.