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Contributor
Contributor
878 Views
Registered: ‎02-27-2018

7-series pcie user_reset_out

Hello,

I'm using 7-series integrated block pcie for my pcie design.  I have an on board 100mhz clock generator (async) for my pcie reference clock.  In my design I use IBUFDS_GTE2 primitive to take in my differential reference clock and turn into single ended clock (sys_clk).  The signal, User_Reset_out, from pcie core is high all the time.  I looked up in the document for this issue and they mentioned that the locked signal from transceiver CPLLLOCK or QPLLLOCK is not locked.  Where do I find CPLLLOCK or QPLLLOCK? and How to get the "locked" signal to lock? Also, in the pcie core I already set PCIE_Async = true.

In addition, if the pcie core didn't receive the reference clock, how come "User_clk_out" is running? I was able to use user_clk_out in my user logic and see in ILA. My impression was "user_clk_out" is depended on the reference clock.

 

Thanks,

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7 Replies
Xilinx Employee
Xilinx Employee
846 Views
Registered: ‎07-26-2012

Re: 7-series pcie user_reset_out

If you enable "Additional Transceiver Control And Sttus Ports" in IP re-customize GUI, Transceiver debug ports appears on the IP. It has pipe_cpll_lock/pipe_qpll_lock ports for checking the lock status of GT pll. And also, the IP has "mmcm_lock" port which should be checked.

Even though these ports are locked, it does not prove that the reference clock is 100% valid. There is also possibility that it is out of the recommended specifications of GT (firstly it is needed to check the clock generator specifications and GT reference clock specifications).

In addition to this, items to be checked are as follows:

1) LTSSM ( Link Training and Status State Machine ) which shows link state of PCIe. user_reset = '1' means the IP does not reach L0 ( link-up state).

2) The cause of not link up may be that the received signal is incorrect. pipe_rxnotintable, pipe_rxdisperr, pipe_rxbusstateus and pipe_debug_* ports are useful to check the rx signal.

 

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Contributor
Contributor
807 Views
Registered: ‎02-27-2018

Re: 7-series pcie user_reset_out

Thanks for your reply!

I follow your recommendations and I can see that both pipe_cpll_lock and pipe_qpll_lock are High which means the reference clock is good. I think RX is having issue and that's why the User_Reset_out is high all the time.  I took a snapshot of the waveform from ILA.

1) User_rst = User_Reset_Out;

2) pcie_ltss = LTSSM = 02

For pipe_rxnotintable, pipe_rxdisperr, and pipe_rxbusstateus, I can't find any user guide document to decode all of the bits meaning. Based on the attached image, can you tell what's wrong with the RX? Am I receiving RX from the PC BIOS?

 

 

 

pcie.jpg
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Contributor
Contributor
786 Views
Registered: ‎02-27-2018

Re: 7-series pcie user_reset_out

I have a question about MGT pins which may related to this post. For MGTPTXP[0:3], MGTPTXN[0:3], MGTPRXP[0:3], and MGTPRXN[0:3], if I want to start out with X1 lane pcie, do you have to follow the pin order by bit 0 (MGTPTXP[0])? or Can you just pick any pin order you want?

 

Thanks!

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Xilinx Employee
Xilinx Employee
771 Views
Registered: ‎07-26-2012

Re: 7-series pcie user_reset_out

Is your using IP "7 Series Integrated Block for PCIe"? If so, pl_tssm_state == "2" means Detect state. If you use "store_ltssm" as trigger signal of ILA, you can see transition of the link state.

Anyway, from the current results, it seems that GT Tx reciver detection failed. If you forcibly advance the detect state with the following AR and link up, The detection function may be the cause.

*the following AR is written for Virtex-6 IP. However, it The idea of swapping signals from GT is the same:
AR#46859
https://www.xilinx.com/support/answers/45859.html


UG476(https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf):
TX Receiver Detect Support for PCI Express Designs

Also, I do not understand the last question well. IP setting is made in multiple lanes, but do you want to force it to operate in single lane?

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Contributor
Contributor
623 Views
Registered: ‎02-27-2018

Re: 7-series pcie user_reset_out

Yes I'm using "7 Series Integrated Block for PCIe. I got to pl_tssm_state = 08, Polling Compliance, Send_Pattern.  I program the fpga thru JTAG and did a soft reset of the PC and I'm still getting pl_tssm_state=08. I follow Xilinx guide and place 0.1uF capacitor on the TX. 

Inside the pcie core, I set up as x1 lane and I can see that on BIOS pick up as x1 but still won't enumerated. Any ideas? 

 

Thanks for your help! 

 

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Xilinx Employee
Xilinx Employee
597 Views
Registered: ‎07-26-2012

Re: 7-series pcie user_reset_out

LTSSMS enters to Compliance state if the lane does not exit from Electrical Idle:

Else Polling.Compliance if either (a) or (b) is true:
(a) not all Lanes from the predetermined set of Lanes from (ii) above have detected an exit
from Electrical Idle since entering Polling.Active.
(b) any Lane that detected a Receiver during Detect received eight consecutive TS1 Ordered
Sets (or their complement) with the Lane and Link numbers set to PAD, the Compliance
Receive bit (bit 4 of Symbol 5) is 1b, and the Loopback bit (bit 2 of Symbol 5) is 0b.

♦ Note: If a passive test load is applied on all Lanes then the device will go to
Polling.Compliance.


If you use an Add-in card inserted in the PCIe slot as like PC/Server, is it the same symptom on another board?

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Contributor
Contributor
573 Views
Registered: ‎02-27-2018

Re: 7-series pcie user_reset_out

I tried it on another PC and got LTSSMS = 0B.

This is a customized design add-in card. I'm wondering if I'm having power problem for GTX transceiver. I have all 8 lanes wired up but temporary only use 1 lane for testing. I have two different voltage regulars for MGTAVCC and MGTAVTT below.

MGTAVCC 1.0v @ 5A max

MGTAVTT 1.2v @ 5A max

Can anyone confirm this is enough power for GTX transceiver? BTW, the device is Kintex-7 160T speed = -1 

 

Thanks! 

 

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