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mwerner2000
Adventurer
Adventurer
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Registered: ‎06-05-2015

7Series PCIe Endpoint Latency Tolerance Reporting supported?

Dear Ladies and Gentlemen,

I am using the PCIe Endpoint with bus master enable. The Endpoint sends read requests to the root complex (main memory) and most of the time everything is fine concerning latency. The average latency is around 30 us (from sending NPR to receiving ALL CPLs). Nevertheless sometimes (every few seconds) the latency is very high (> 1ms) for a few requests which triggers the completion timeout. Our application requires a max latency of 60 us, which can be met most of the time. There is also a mechanism to prevent overprovisioning and/or congestion. Nevertheless the root cause of this latency could be manifold and is assumed to be in the root complex (memory access, port arbitration etc.) and Latency Tolerance Reporting could help to prioritize requests from my endpoint.

Does the 7Series PCIe Endpoint support the Latency Tolerance Reporting Mechanism described in Section 6.18 in the PCIe 2.1 Spec?

When configuring the core using Vivado there is no option to modify the LTR Capabilities. Using LTR could potentially solve the problem, because LTR would encourage the Root Complex to meet the timing requirements.

 

Thank you very much in advance.

 

Best regards,

Martin

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kurihara
Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

In the case of 7 series IP, I think it is necessary to configure and send message packets on the user logic side. The IP itself does not build the message packet.

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mwerner2000
Adventurer
Adventurer
388 Views
Registered: ‎06-05-2015

Dear kurihara,

 

thanks for the reply. Well the latency report mechanism requires a the Latency Tolerance Reporting Capability register space as well as the LTR Message. The config space can only be provided by the core itself. It is also neccesary to set the LTR Supported flag in the device capability register 2, which doesn't seem to be possible in the IP config dialog. Since there is no option to configure this (unlike e.g. AER, which does have a corresponding config space if configured), I assume that this feature is not supported by the core. There is also no mentioning in the user manual.

 

Best regards,

Martin

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