Am currently working on 7th series Integrated PCIe(EndPoint) for AC701(Artix 7) Board.
I am able to simulated the example design for single BAR enabled and it is fine, but when i enable 3 BAR i am getting confused as
1. BAR is basically Base address for some memory which is assigned by the Root Port, how will i know that the address assigned is to that particular BAR?
2. And for read request from Root Port which is the address to which the data is to be written from end point.
3. By enabling BAR will the BRAM enabled by the core or should we instantiate the BRAM?.
4. Any advice on memory mapping would help a lot.
Thanks and Regards,