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Visitor
Visitor
8,402 Views
Registered: ‎09-23-2011

A pcie in-band hot reset or link disable will induce the assertion of trn_reset_n?

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Hi all,

I am using Virtex6 integrated block for PCIE, the version is 1.6.

According to the user guide It seems a pcie in-band hot reset or

  link disable will induce the assertion of trn_reset_n, is it?

 

And how can I trigger an in-band hot reset of link disable in the pcie link?

 

Thank you very much for any information.

Yan

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Visitor
Visitor
10,457 Views
Registered: ‎09-23-2011

According to Xilinx product applications engineer, the in band hot reset and link disable will not induce trn_reset_n's assertion. Hope the UG517 is going to be fixed.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-06-2010

When you say "trigger" I'm guessing you're talking about chipscope.  I why not trigger off of trn_reset_n deasserting?

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Visitor
Visitor
8,389 Views
Registered: ‎09-23-2011
Hi, luisb
Let me clarify this problem.
Now I am not sure whether a in-band hot-reset or link disable will induce the assertion of trn_reset_n. So I want the simulate a hot reset or link disable. Could you help me to point out how to simulate them?
Thank you very much.
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Visitor
Visitor
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Registered: ‎09-23-2011

Hi all,

I have simulated the hot reset and link disable by control the RC config register

and the core logic signals, pl_received_hot_rst and trn_lnk_up_n, have been asserted.

But it is amazing the trn_reset_n has not been asserted in both hot reset and link disable circumstance.

Who can tell me why?

Thank you very much.

 

Yan

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Anonymous
Not applicable
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I agree that UG517 isn't clear on whether or not an in-band Hot Reset or Link Disable causes trn_reset_n to be asserted. In Table 2-10 (page 32) in the description for trn_reset_n it says that Hot Reset or Link Disable causes trn_reset_n to be asserted. However, in the "Clocking and Reset of the Integrated Block Core" section (page 184) it lists 3 conditions that cause trn_reset_n to be asserted and none of them are related to Hot Reset or Link Disable. The 3 conditions are Fundamental Reset (Cold/Warm), Core wrapper PLL losing lock, and Transceiver PLL losing lock.

Can anyone provide more info as to whether Hot Reset or Link Disable actually cause trn_reset_n to be asserted? My question is related to the 1.7 version of the Virtex-6 FPGA Integrated Block for PCI Express.
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Visitor
Visitor
10,458 Views
Registered: ‎09-23-2011

According to Xilinx product applications engineer, the in band hot reset and link disable will not induce trn_reset_n's assertion. Hope the UG517 is going to be fixed.

View solution in original post

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