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Registered: ‎02-11-2020

AR71453 - how to build bitstream for ST and MM


Vivado 2019.2.1

Two questions regarding creating/building bitstreams for performing benchmark testing described in the AR71453:

A) Pls confirm that these are the expected steps for building the Streaming bitstream described in the AR71453

  1. Create a new project: "prj_qdma_perf_ST"
  2. Select "part' on target board: xczu28dr-ffvg1517-2-e
  3. Add IP from IP Catalog: QDMA
    1. Configure QDMA IP per AR71453: Lanes=x8 (for my board), Enable SRIOV, PF=4, Prefetch Cache Depth=64, CMPT Coalesce Max Buffer=32 (defaults for everything else)
  4. "Generate Output Products" -> "Out of Context" -> "Ok" (~15min)
  5. TCL console
    1. Although 'specific' to 2019.1,, this seems applicable for 2019.2.1:
      1. set_property CONFIG.performance_exdes {true} [get_ips qdma_0]
    2. What is alarming about this is that CONFIG.performance_exdes is for C2H/H2C Streaming-only.
    3. So how was the Memory Map tested as detailed in AR71453? If a custom project was required, then please state that this is the case in AR71453.
  6. Right-mouse-click on "qdma_0", and select "Open IP Example Design", and check "Overwrite existing example project".
  7. In the newly generated example project called "qdma_0_ex", select: "Generate Bitstream" (~15 min for OOC (again!?) + ~25 min)
    1. A bitstream is created.
    2. Program the FPGA via JTAG
    3. Restart host
    4. lspci - fails to be shown, because the PCIe pins were not included in the .xdc file.
  8. Added PCIe pinout information of the target board to the example design's .xdc file.
    1. "Generate Bitstream"
    2. Program the FPGA JTAG
    3. Restart host
    4. $ lspci | grep Xilinx
      b3:00.0 Memory controller: Xilinx Corporation Device 9038
      b3:00.1 Memory controller: Xilinx Corporation Device 9138
      b3:00.2 Memory controller: Xilinx Corporation Device 9238
      b3:00.3 Memory controller: Xilinx Corporation Device 9338


B) While the AR71453 provides performance measurement for the Memory Map, it doesn't specify the QDMA IP settings or describe how to create a bitstream. Please provide such details for recreating a bitstream to benchmark QDMA configured for MM.

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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007

when you configuration the IP as Memory Map or Memory Map and stream, using the same example design, you  will be able to test the performance using the driver and the apps provides (in scripts folder)

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