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Participant saicgpt
Participant
445 Views
Registered: ‎06-26-2008

AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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I have a PCIe XDMA example running on VC709 which i compiled using 2018.3. The H2C is 256bit AXI-MM interface which is connected to a 256-bit wide x 512 BRAM. The problem I see is that the BRAM controller is not auto-incrementing BRAM write addresses for a AXI4 transaction which is burst write.

The controller is setup as:

AXI BRAM Controller Setup.JPG

The ILA capture below shows an AXI-MM transaction with AWLEN= 0x0F, AWSIZE=32bytes, at AWADDR=0x1000.  It should generate a burst transaction of 16 256-bit words on the BRAM.  But if you notice the SLOT1_BRAM_addr stays fixed at 0x1000 throughout the burst (BRAM_en='1').

AXI_MM Write Burst BRAM Controller.JPG

Shouldnt't the BRAM address increment sequentially by 32 during the entire burst? (i say 32 because its 256-bit BRAM width, so address shoudl go 0x1000, 0x1020, 0x1040.. and so on..)

Thank you in advance.

1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
230 Views
Registered: ‎07-26-2012

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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Can you check the register bit in the following? If the bit is set, it makes the IP in non-incrementing address mode.

View solution in original post

fixmode.png
6 Replies
Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎07-26-2012

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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If I don't misunderstood the question, AXI bursts will give only the starting address, so the behavior is correct I think. Please read the written data to confirm.

aci_burst.png
Participant saicgpt
Participant
340 Views
Registered: ‎06-26-2008

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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Hello,

Thank you for the reply.  You are correct that on AXI side, AXI bus will on give the starting address.  But on the BRAM side, SLOT1_BRAM_Addr (6th waveform from the bottom) should increment for each clock cycle while SLOT1_BRAM_en is high.  If you notice BRAM_Addr, it stays at 0x1000.  Refer to this example shown in PG078 guide.

Capture.JPG

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Xilinx Employee
Xilinx Employee
283 Views
Registered: ‎07-26-2012

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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Yes.As the waveform of the PG, address will increment. Is the memory space enough to store incremented address data?

 

BRAM_addr.png
Participant saicgpt
Participant
259 Views
Registered: ‎06-26-2008

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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Thanks for the reply.

Yes, i have 16K BRAM (as indicated by the BRAM_Addr which is [13:0] bus).  The last waveform you posted is what I was expecting to see on the BRAM_Addr port, but all i see is a fixed address at 0x1000 for the entire time when BRAM_en is high.

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎07-26-2012

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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Can you check the register bit in the following? If the bit is set, it makes the IP in non-incrementing address mode.

View solution in original post

fixmode.png
Participant saicgpt
Participant
209 Views
Registered: ‎06-26-2008

Re: AXI BRAM Controller doesn't auto-increment BRAM addresses for burst transaction

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Hello,

That was it!   The problem wasn't really the BRAM controller,  but how H2C was generating the AXI-MM transactions.  I set bit 25 of the control 0x4 to a '0', and now i am getting incrementing BRAM addresses.

Thank you very much for your support.