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fernands
Visitor
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Registered: ‎07-16-2019

AXI Bridge PCIe user clock

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Hi everyone,

I have a quick and hopefully straightforward answer regarding using the AXI Bridge for PCIe Gen3 Subsystem: the ip does not seem to offer a port with an user clock to be use externally. I am assuming that I could use the axi_aclk, but as mention in the official documentation:

"Note: The axi_aclk output should not be used for the system clock for your design. The axi_aclk isnot a free-run clock output. As noted, axi_aclk may not be present at all times."

Any clarification is more than welcome. Thanks in advance!

 

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seamusbleu
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Registered: ‎08-12-2008

Yes, the Axi_aclk "replaces" the user_clk that was in non-axi pcie bridges.

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mattwaltz
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Registered: ‎06-05-2017

When using the AXI bridge, usually AXI interconnects are used. The axi_aclk should connect to the corresponding master and slave interfaces on these interconnects but the AXI Interconnect's clock and reset should be derived external to the IP (This is the ACLK and ARESETN ports).

The "system" clock that the note is referring to is the clock that drives the majority of IP, such as softcore processors and other peripherals.

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fernands
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Registered: ‎07-16-2019

 Thanks for the reply. Yes, this is how I am using the axi_aclk with the different AXI slaves I have to address the different PCIe Bars; I was asking about the user clock that normally is provided as an output of the Xilinx PCIe core block. For instance, in the documentation for the Ultrascale PCie Integrated block (without the AXI Bridge) on page 59 the user_clk is described. Page 103 also describes the port as

user_clk is simply the main internal clock for the PCIe IP core. Use this clock to synchronize any user logic that communicates directly with the core.

My question is, in the AXI Bridge for PCI Express, is the axi_aclk the clock port to use for this logic? I am assuming it is, even more so since looking into the code generated by the module the port is associated with the USER generic.

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mattwaltz
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Adventurer
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Registered: ‎06-05-2017

You asked about the AXI Bridge core; not the PCIe Integrated Block. While they may generate the same clock in the same way; in your case you should use the axi_aclk for the master and slave interfaces and the axi_ctrl_aclk for the control interface. I'm not even sure why you are bringing up the integrated block.

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seamusbleu
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Registered: ‎08-12-2008

Yes, the Axi_aclk "replaces" the user_clk that was in non-axi pcie bridges.

<== If this was helpful, please feel free to give Kudos, and accept as Solution if it answers your question ==>

View solution in original post