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Adventurer
Adventurer
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Registered: ‎02-08-2016

AXI Bridge for PCI Express Gen3 Subsystem used in XCVU440 - Cannot select GTH QUAD 226

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AXI Bridge for PCI Express Gen3 Subsystem (3.0) used in XCVU440 - Cannot select GTH QUAD 226

 

Hi the AXI Bridge for PCI Express Gen3 Subsystem (3.0)  wizard does not let me select anything but the GTH QUAD 227 for PCIe block location X0Y3 . I need to select GTH QUAD 226 to correctly connect PCIe for my hardware PCIe pinout.

 

Should I manually hack the output file produced by the wizard to change this?

 

See attached screenshot

 

Thanks

 

Simon

pcie_EP_GTH_select.png
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Adventurer
Adventurer
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Registered: ‎02-08-2016

Ok this is how to do this.

 

generate IP and then substitute required GTH_QUAD_nnn string into all .xci, .xml and .v files.

 

Then find all the .xdc for the IP and subsitute the correct set_property LOC GTHE3_CHANNEL_XnYm   expression.

 

Simon

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Adventurer
Adventurer
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Registered: ‎02-08-2016

...furthermore I have successfully used the GTH QUAD 226 before, when I used the PCIe PHY IP wizard . see screenshot below.

 

 

pcie_PHY.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @simonh_bwt,

 

Which package are you using of the VU440? 

 

The reason you can select this in the PHY IP is that the GT Quads are used standalone in that mode, and not tied to a specific hardblock.   Often, the reason an adjacent quad may not be selectable with the full UltraScale Integrated Block IP is that the Quad is in a different SLR than the hardblock is located. 

 

 

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Moderator
Moderator
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Registered: ‎02-16-2010
@simonh_bwt,

Could you get any solution for your problem? To help by reviewing your use case, please provide the full device part number along with the package.
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Adventurer
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Hi Thanks for your message - I was away last week rock climbing hence I did not reply.

 

The package part we are using is : xcvu440-flga2892-2-i   , or xcvu440-flga2892-1-i

 

So I think the GTH QUAD 226 is living in the second SLR up - I think that is SLR1

 

Thanks

 

Simon

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Moderator
Moderator
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Registered: ‎02-16-2010

I reviewed your issue related to the location of PCIe and GT quad location available in ug575, page 110. The GT quad 226 you have selected is a middle quad of the SLR. PCIe blocks are present on top and bottom of the SLR. You can find that GT quad which is placed in the middle of the SLR is not supported with any PCIe blocks in the device. Similar to quad 226, you can find quad 231 and 221 are not supported with any PCIe hard blocks.

 

The reason for this can be that the GT quad 226 is far from the PCIe hard blocks to ensure the timing related requirements are met.

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Adventurer
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Registered: ‎02-08-2016

Hi Venkata

 

Thanks for your reply. What you say makes sense - however the evidence of previous builds I have done suggests you can hook a PCIe to I/O Bank 226. Please see the attached screenshot "Bank226"

 

Here you can see the layout of a previous build I completed that had a functional PCIe. Please note that the GTHE3_CHANNEL_X0Y28 lives in Clock region X8Y7 of SLR1, the I/O pins are connected to Bank 226.

 

The constraints file for this build included the lines below [ I think this just swaps the PCIe channels 1 & 0 ] :

 

# LOC for PCIe GTHE Channel and clocks
set_property LOC GTHE3_CHANNEL_X0Y29 [get_cells {bh2_fpga_core/bh2_core/bh2_mod_0/m_bh2_sys_hydra_0/m_bh2_system_0/m_bh2_sys_core_0/m_pcie_0/m_bh2_pcie_core_wrap1_0/m_bh2_pcie_wrap/i_bh2_pcie_subsystem/i_dwc_pcie_subsystem/pcie_phy_0_i/inst/Uscale_gt.us_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie_phy_0_gt_i/inst/gen_gtwizard_gthe3_top.pcie_phy_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[7].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]


set_property LOC GTHE3_CHANNEL_X0Y28 [get_cells {bh2_fpga_core/bh2_core/bh2_mod_0/m_bh2_sys_hydra_0/m_bh2_system_0/m_bh2_sys_core_0/m_pcie_0/m_bh2_pcie_core_wrap1_0/m_bh2_pcie_wrap/i_bh2_pcie_subsystem/i_dwc_pcie_subsystem/pcie_phy_0_i/inst/Uscale_gt.us_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie_phy_0_gt_i/inst/gen_gtwizard_gthe3_top.pcie_phy_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[7].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[1].GTHE3_CHANNEL_PRIM_INST}]

So you can see that the PCIe In this case - I believe it is X0Y3 - is connected to bank 226 and GTHE Quad 226.

 

I have a second question to help this query.

What is the correspondence between GTH Quad nnn , and Bank nnn ? Is it that GTH Quad nnn is always attached to Bank nnn ?

 

and finally the figure 1-164 see attached, seems to indicate that Quad 228 rather than Quad 226 is not available.

 

Thanks 

 

Simon

Bank226.png
XCVU440Banks.png
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Moderator
Moderator
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Registered: ‎02-16-2010
Yes. IO bank number and GTH quad number is same for GT pins. I think it is different nomenclature for the GT pins.

GTH Quad nnn is always attached to Bank nnn.
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Adventurer
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Registered: ‎02-08-2016

Hi Venkata

 

Please refer to my previous message - dated 04-24-2018 03:09 AM.

Attached to that is a screenshot proving that I can in fact sometimes use GTH_QUAD_226 .

 

So your previous comment about GTH_QUAD_226 is incorrect. I think the documentation is also incorrect.

Please clarify this issue.

 

Thanks SImon

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Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi Simon,

 

Per our documentation on the subject, the locations that are selectable have been tested and qualified.  These are the locations that will meet timing.  Users have the option to select a different quad manually, but any link issues in the future or timing closure issues are left to the user if they do not use one of the tested and qualified locations.

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Adventurer
Adventurer
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Registered: ‎02-08-2016

Thanks for your response

 

Further research on my part seems to indicate that more recent version of the PCIe IP prevent certain GTH_QUAD s being selected. However older versions did not.

 

I am running my PCIe blocks at GEN1/2 and my board hardware uses GTH_QUAD_226 pinout. Therefore in order to support legacy bitstreams I must keep to the same PCIe pinout.

 

To do this I am forced to use older version of the IP with later versions of Vivado.

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Adventurer
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Registered: ‎02-08-2016

Ok this is how to do this.

 

generate IP and then substitute required GTH_QUAD_nnn string into all .xci, .xml and .v files.

 

Then find all the .xdc for the IP and subsitute the correct set_property LOC GTHE3_CHANNEL_XnYm   expression.

 

Simon

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