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Observer tomo_naga
Observer
433 Views
Registered: ‎08-02-2017

AXI MM - PCIe IP: Register mapping

Hi.

 

I'm trying to design PCIe root complex in Zynq by using AXI MM PCIe bridge IP.

My design goal is that Zynq can recognize a NIC like as introduced below link.

http://www.wiki.xilinx.com/ZynqMP+Linux+PL+PCIe+Root+Port

 

The environments:

 Boards: ZC706, PCIe FMC Module (Hightechglobal), NIC

 Tool: Vivado 2018.1

 

First, I tried to configure the HW using axi_pcie and axi_cdma based on the steps shown in below link.

http://www.fpgadeveloper.com/2016/04/zynq-pci-express-root-complex-design-in-vivado.html

 

The addresses are assigned as follows:

address_editor.png

 

The implementation could be done and the HDF was exported for SDK.

However, there is a difference between my thought and SDK result.

The PCIe configuration space was assigned to s_axi interface, namely the address 0x6000_0000 as follows:

sdk_axi_pcie_reg.png

 

Is the configuration space normally assigned to s_axi_CTL, namely the address 0x5000_0000?

I tried to execute the sample program (xaxipcie_rc_enumerate_example.c) but the link is not up because of this assignment.

 

Does anyone have solutions?

Or please correct me if I'm wrong.

 

Thank you in advance.

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1 Reply
Xilinx Employee
Xilinx Employee
366 Views
Registered: ‎08-06-2008

Re: AXI MM - PCIe IP: Register mapping

Hi,

Have you tried swapping the offset address between S_AXI and S_AXI_CTL?

Thanks
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