AXI MM - PCIe IP: Register mapping

tomo_naga · ‎06-11-2018

Hi.

I'm trying to design PCIe root complex in Zynq by using AXI MM PCIe bridge IP.

My design goal is that Zynq can recognize a NIC like as introduced below link.

The environments:

Boards: ZC706, PCIe FMC Module (Hightechglobal), NIC

Tool: Vivado 2018.1

First, I tried to configure the HW using axi_pcie and axi_cdma based on the steps shown in below link.

The addresses are assigned as follows:

The implementation could be done and the HDF was exported for SDK.

However, there is a difference between my thought and SDK result.

The PCIe configuration space was assigned to s_axi interface, namely the address 0x6000_0000 as follows:

Is the configuration space normally assigned to s_axi_CTL, namely the address 0x5000_0000?

I tried to execute the sample program (xaxipcie_rc_enumerate_example.c) but the link is not up because of this assignment.

Does anyone have solutions?

Or please correct me if I'm wrong.

Thank you in advance.

deepeshm · ‎06-20-2018

Hi,

Have you tried swapping the offset address between S_AXI and S_AXI_CTL?

Thanks

Re: AXI MM - PCIe IP: Register mapping