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ttocco
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Registered: ‎11-26-2018

AXI Memory Map to PCI Express Gen2

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 We are having difficulty writing data from our PCIe endpoint (XC7Z015) to a Root Port (NI Controller) via the S_AXIS bus on the AXI MM to PCIe IP.  Performing 32-bit write(s) across the M_GP1 bus to the S_AXIS are acknowledged by the AXI response bus, but they are not being received at the HOST.  We are monitoring the control registers available through the S_AXIS_CTL interface, but don't see any transfer errors. How can we determine if the MemWr packet has been successfully sent?

We are able to successfully read and write from the Host side to the Endpoint. Just not from the Endpoint to the Host side.

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liy
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Please make sure bus master bit in command register is set 

 

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liy
Xilinx Employee
Xilinx Employee
313 Views
Registered: ‎08-02-2007

Please make sure bus master bit in command register is set 

 

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ttocco
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Registered: ‎11-26-2018

Yes, we verified the command bit is set. 

 

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