04-12-2019 12:45 AM
i've got a question regarding to a PCI endpoint Design. I want to read a constant from GPIO but instead of reading my magic number (DEADBEEF), i only read 0xFFFFFFFF.
PCIe BAR config.
When i'm using the XDMA IP and connect the GPIO with the AXI Lite i can read my constant, but not with the AXI MM to PCIe IP.
What i'm doing wrong?
04-12-2019 07:28 AM
Does this working in simulation?
If it is in hardware you are checking in, have you checked if the memory read and the completion for the reads are shown on different interfaces of the blocks you have in your design? You can do this by inserting system ILA. Also, make sure you are reading the right memory location. Your address translation parameter has 0x40000000. Any address you use from the host to read will being with 0x4.... You should make sure the read address is going to the correct destination.
04-12-2019 08:07 AM
I just checked it in HW with rweverything.
tried it with different adresses like 0x00000000 and 0x50000000 but it was the same.
I set up a view debug probes on the AXI bus but it seemed to be dead.
04-16-2019 08:13 PM
You will get all F's if your AXI slave doesn't respond. Instance a System ILA on both of the the AXI buses (switch master, switch slave) and take a look at your transction. Probably what you will see is the switch master port is getting a SLVERR response on RRESP. The switch will do that if the requested address isn't mapped properly.
If you're using a Linux system, try using 'pcimem' which is a simple utility to peek/poke PCIe address space. Get it here: https://github.com/billfarrow/pcimem
11-19-2019 03:35 AM
I am seeing exactly this as well.
DMA access seems fine; I can execute the run_tests.sh script or the performance test and everything passes. I can also read registers using the device /dev/xdma0_control. Any access to /dev/xdma0_user just returns 0xffffffff
Did you manage to find the problem?
I have been trying several different ways to construct the slave on the AXI-Lite bus:
a) using the IP generator to build a slave register file, and attaching to the bus in RTL
b) using the block diagram subsystem automation to build another memory attached to the AXI-Lite bus.