AXI bridge PCIe IP core sys_clk and sys_clk_gt

[Anonymous]

Hello,

I would like to know which clock source may I use to connect sys_clk and sys_clk_gt of an AXI bridge PCIe IP core ?

Is it possible to connect this two clock to the same 100 MHz internel clock generated from the zynq US+ mpsoc (IOPLL) ?

Thanks

H.K

[venkata]

sys_clk is required to be driven from an oscillator from the board (or) slot clock coming from Root Port. Do you have any of these options with your design?

[Anonymous]

I use a clock (IOPLL) driven from the PS part of zynq ultrascale+

[venkata]

IOPLL from PS cannot be used to source sysclk of PCIe.

[Anonymous]

what about clk_gt ? can I use IOPLL from PS ?

[venkata · Accepted solution]

Please refer to Table 2-2 of PG194.
sys_clk --
UltraScale+: Dynamic reconfiguration port (DRP) Clock
and Internal System Clock (Half frequency from
sys_clk_gt frequency if PCIe Reference Clock is 250 MHz,
otherwise same frequency as sys_clk_gt frequency).
Should be driven by the ODIV2 port of reference clock
IBUFDS_GTE4.

sys_clk_gt --
UltraScale+: Should be driven from the O port of
reference clock IBUFDS_GTE4.