03-16-2018 12:46 AM
Hello,
I would like to know which clock source may I use to connect sys_clk and sys_clk_gt of an AXI bridge PCIe IP core ?
Is it possible to connect this two clock to the same 100 MHz internel clock generated from the zynq US+ mpsoc (IOPLL) ?
Thanks
H.K
03-27-2018 09:29 AM
03-16-2018 09:35 AM
03-19-2018 12:43 AM
I use a clock (IOPLL) driven from the PS part of zynq ultrascale+
03-23-2018 05:16 PM
03-27-2018 02:40 AM
what about clk_gt ? can I use IOPLL from PS ?
03-27-2018 09:29 AM