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eibach
Visitor
Visitor
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Registered: ‎07-02-2018

AXI bridge for PCIe performance

I have implemented an AXI bridge for PCIe (PG194) connected to DDR4 memory on my KCU105 evalboard. I am wondering what performance I can expect from this solution. I am doing a PCIe peer to peer transfer from another card on the bus to the KCU105. The other card is connected Gen3 x16 and can saturate the link with 13.5 Gbyte/s when reading from main memory. But reading from the KCU105 only results in up to 3 Gbyte/s, where I would expect (and need) at least 6 GByte/s. Is this to be expected?

And no, using the Xilinx DMA subsystem IP is not an option, because the other card on the bus does not map the memory to PCIe. But I have verified using the DMA subsystem IP that the KCU105 can deliver at least 6 Gbyte/s from DDR4 to main memory. 

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bethe
Xilinx Employee
Xilinx Employee
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Registered: ‎12-10-2013

Hi @eibach,

 

Can you please provide a bit more information on your AXI Bridge configuration?  What speed / width is it programmed at?  What AXI Bus speed / width?  What size transfers are you doing?  What is the system MPS / MRRS on the KCU105.

 

 

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eibach
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Registered: ‎07-02-2018

The bridge is from PCIe 8GT/s x8 to 256bit 250 MHz AXI. I attached the exported block design for your reference. MPS is 512 byte.

 

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