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Newbie
Newbie
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Registered: ‎04-01-2020

AXI-to-PCIe reads all FF's from BAR 1

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Hi all,

I can't seem to read anything but FF's from PCIe BAR1 address space when using the IP block for the AXI4-to-PCIe interface.  My hardware works fine with an older 2016 .bit file, so I know my problem is in Vivado 2019 or my VHDL code.   Please see attached PDF file for more-detailed information and screenshots.

Thanks in-advance for any advice you can offer !!

Hope you are surviving the COVID-19 pandemic so far

Erik

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Newbie
Newbie
442 Views
Registered: ‎04-01-2020

Hi all,

after more wrestling with the configuration settings of the AXI4-to-PCIe IP block, I was able to solve my own problem in my design.  The solution required throwing out the auto-assigned addresses that the silly "Address Editor" had automatically assigned to my BAR1 slaves, and manually entering sane values for the start address of each BAR1 slave myself.  Once I had decent addresses near the bottom of the BAR1 address range (instead of the auto-generated ones at strange offset values) I could read them just fine.  See attached screenshot.

Thanks for those who viewed my issue and gave it any thought at all

Erik

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good_bar1_address_manual_assignments.PNG
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1 Reply
Highlighted
Newbie
Newbie
443 Views
Registered: ‎04-01-2020

Hi all,

after more wrestling with the configuration settings of the AXI4-to-PCIe IP block, I was able to solve my own problem in my design.  The solution required throwing out the auto-assigned addresses that the silly "Address Editor" had automatically assigned to my BAR1 slaves, and manually entering sane values for the start address of each BAR1 slave myself.  Once I had decent addresses near the bottom of the BAR1 address range (instead of the auto-generated ones at strange offset values) I could read them just fine.  See attached screenshot.

Thanks for those who viewed my issue and gave it any thought at all

Erik

View solution in original post

good_bar1_address_manual_assignments.PNG
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