I have tried to follow an example design, but unfortunately the example designs only show this S_AXI_B port being used in "Root Port" mode, but do I really require this?Is this port not usable in endpoint mode?
I ask because if we look at Table 20 (p.40) of pg194  we see the "bridge enable" bit supposedly allows the AXI2PCI functionality. However this register is not accessible given the statement above saying "For non-Root Port cores, reads return 0 and writes are ignored".
If this is the case then how can I use this port to write directly to memory? Do I have to set it up as a root port and thus manually configure the pci device with user logic before enumeration?
Any suggestions where I can go from here would be greatly appreciated!