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Registered: ‎10-06-2017

AXI2PCI no AXI Write Response, AXI Slave Bridge in Endpoint mode.


I am having troubles getting the DMA/Bridge Subsystem (xdma 4.1, set up in bridge, endpoint mode) to write PCI transactions to the host.

When I perform a write into the S_AXI_B port I get no B response back. I do not get SLVERR response or anything like that suggesting invalid addresses etc. Simply nothing comes back...

When I insmod the XDMA driver ip and perform an lspci, I see that the bus-mastering has been enabled:

81:00.0 Communication controller: Xilinx Corporation Device 2808
Subsystem: Xilinx Corporation Device 0007
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-

I have tried to follow an example design, but unfortunately the example designs only show this S_AXI_B port being used in "Root Port" mode, but do I really require this?Is this port not usable in endpoint mode?

I ask because if we look at Table 20 (p.40) of pg194 [1] we see the "bridge enable" bit supposedly allows the AXI2PCI functionality. However this register is not accessible given the statement above saying "For non-Root Port cores, reads return 0 and writes are ignored".

If this is the case then how can I use this port to write directly to memory? Do I have to set it up as a root port and thus manually configure the pci device with user logic before enumeration?

Any suggestions where I can go from here would be greatly appreciated!




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