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Registered: ‎06-07-2010


A problem I have been facing with the Xilinx PCIe IP has been to upgrade the provided PIO reference design to a more general one, supporting burst mWr and mRd transactions.

This has involved writing code to deal with the Local Link interface and implement the transaction layer protocol, with an obvious overhead in terms of design and verification.


I have been thinking of using the AXI4 streaming PCIe IP (e.g. as described in ug672) with the AXI4 DMA IP (ds781) and building the user IF (FIFOs/Registers) out of the AXI4 Memory Mapped IF provided by the DMA IP.

The typical design requires the use of a Microblaze for configuration purposes, which is an additional overhead....


Can anybody contribute suggestions/tips on this topic?


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Xilinx Employee
Xilinx Employee
Registered: ‎07-16-2008


The short answer is that for PCIe designs get started today with Xilinx Connectivity Targeted Design Platforms. and


These Targeted Design Platforms contain all of the key peices for customers to develop their own connectivity designs  including RTL source code reference designs where you can tailor the design to your application, PCIe DMAs, PCIe drivers, PCIe form factor boards, download cables, software, Xilinx Tools and more.  This is the best, fastest, and most economical way to start a project with PCIe.


To talk a little bit about PCIe cores, example designs and DMAs:


PCIe Cores:

  • TRN
    • We now refer to as the “legacy” user interface
    • Will be supported for the Virtex-6 and Spartan-6
    • Will not be supported on the 7-Series
    • Is versioned with a 1.x in CoreGen
  • AXI4-Stream interface
    • Very similar to the legacy TRN interface
    • Best used for high-performance applications that want to maximize the bandwidth of PCIe
    • Available starting in IDS12.3 for Virtex-6 and Spartan-6
    • Core version numbers are 2.x (Legacy i/f is versioned 1.x)
    • PCIe AXI User Guide contains a migration guide to help customers modify their user application to be used with the AXI4-Stream i/f on the PCIe core
      1. This has been designed to help minimize impact to existing customers
    • Receives all critical and other beneficial enhancements
    • Recommended for all new designs
  • PLB46_PCIe
    • Legacy Memory Mapped interface
    • Available only through EDK and Xilinx Platform Studio
    • Supports x1 Gen1 only
    • Will only receive critical updates
    • Supported for the Virtex-6 and Spartan-6 products
    • Will not be supported in the 7-Series
  • AXI4 Interface (Memory Map)
    • Will be available only through EDK and Xilinx Platform Studio
    • Will be available starting in IDS13.2
    • Enhancements will happen through the IDS13.x cycle
    • Will support greater link widths and features
    • Will support Virtex-6 and Spartan-6 initially
    • 7-Series support will be added in subsequent releases


Programmed I/O & DMA:

  • Programmed I/O (PIO)
    • Good for getting a card up and running
    • Good for Debugging
    • Good for a processor initiated reads and writes of an FPGA
  • Alliance Partner DMA
    • Use the connectivity kits for your PCIe designs
      • These are PCIe based designs to help quickly get designs to market
      • Drivers,  flexible RTL design, source code, and more are provided
      •  DMA is included as an evaluation in V6 or as a full license in S6
    • Save time, money, & resources with an Alliance Partner DMA
      • Great products and amazing value
  • XAPP 1052 and XAPP 859
    • Xilinx DMA reference designs
    • Designed to push the Xilinx PCIe core to the limits
    • Designed to provide a starting point for customer development of their own DMA
    • Expect to spend time tailoring the DMA to the application and for tuning
    • Recommend Alliance Partner DMA for time to market and EOU
  • MPMC & Central DMA
    • For EDK users there is PLB46 and AXI4 components for DMA and data movement
    • These will be released in the IDS13.x cycle
    • Designed for MicroBlaze based designs
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