01-29-2011 03:00 AM
A problem I have been facing with the Xilinx PCIe IP has been to upgrade the provided PIO reference design to a more general one, supporting burst mWr and mRd transactions.
This has involved writing code to deal with the Local Link interface and implement the transaction layer protocol, with an obvious overhead in terms of design and verification.
I have been thinking of using the AXI4 streaming PCIe IP (e.g. as described in ug672) with the AXI4 DMA IP (ds781) and building the user IF (FIFOs/Registers) out of the AXI4 Memory Mapped IF provided by the DMA IP.
The typical design requires the use of a Microblaze for configuration purposes, which is an additional overhead....
Can anybody contribute suggestions/tips on this topic?
02-07-2011 01:42 PM
The short answer is that for PCIe designs get started today with Xilinx Connectivity Targeted Design Platforms.
These Targeted Design Platforms contain all of the key peices for customers to develop their own connectivity designs including RTL source code reference designs where you can tailor the design to your application, PCIe DMAs, PCIe drivers, PCIe form factor boards, download cables, software, Xilinx Tools and more. This is the best, fastest, and most economical way to start a project with PCIe.
To talk a little bit about PCIe cores, example designs and DMAs:
Programmed I/O & DMA: