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Visitor luke84
Visitor
10,835 Views
Registered: ‎12-31-2007

About PCI Express example-design

 Hello! I met a problem when I read the example-design code in  "PIO_64_RX_ENGINE.v " file which is generated with the PCI Express IP Core .
 
   Here are  the Verilog HDL code which I cut from that file:
 
        `PIO_64_RX_MEM_WR64_DW1DW2 : begin
              if (!trn_rsrc_rdy_n) begin
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                wr_addr_o      <= #`TCQ {region_select[1:0],trn_rd[10:2]};
                state          <= #`TCQ  `PIO_64_RX_MEM_WR64_DW3;
              end else
                state          <= #`TCQ `PIO_64_RX_MEM_WR64_DW1DW2;
            end

            `PIO_64_RX_MEM_WR64_DW3 : begin
              if (!trn_rsrc_rdy_n) begin
                wr_data_o      <= #`TCQ trn_rd[63:32];
                wr_en_o        <= #`TCQ 1'b1;
                trn_rdst_rdy_n <= #`TCQ 1'b1;
                state        <= #`TCQ `PIO_64_RX_WAIT_STATE;
              end else
                 state        <= #`TCQ `PIO_64_RX_MEM_WR64_DW3;
        
            end
  
   I know  that these are the states to write  data from the data packet.But why do you only do the writing in the  `PIO_64_RX_MEM_WR64_DW3  state(I signed the action in red),but not in the  `PIO_64_RX_MEM_WR64_DW1DW2  state.
   Could you explain it ,please?Thanks.
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4 Replies
Xilinx Employee
Xilinx Employee
10,817 Views
Registered: ‎08-07-2007

Re: About PCI Express example-design

Hi,

These states are used when the incoming packet is a 64-bit addressable memory write (MWr64). A MWr64 has 4 Dwords of header in the packet before the data starts. See Figure 2-13 on page 62 of the PCIe Spec (sec 2.2.7 of v1.1)

Also note that the data is being provided 64 bits at a time to the user on the trn_rd[63:0] bus.

The FSM starts in PIO_64_RX_RST_STATE where the first two DWords of the packet are captured and decoded. Based on this, it then goes to PIO_64_RX_MEM_WR64_DW1DW2 where the second two Dwords of the pacet which is the 64 bits address is captured. Then it goes to PIO_64_RX_MEM_WR64_DW3 where the first DWord of data is captured.

I think the confusion is because the state names (DW1, DW2, DW3) are not actually right if you align it with the packet Dwords. Not sure why that is and had not noticed it until now.

-John
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Visitor luke84
Visitor
10,754 Views
Registered: ‎12-31-2007

Re: About PCI Express example-design

Thank you very much!You have explained it so clear.
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Visitor gprabodha
Visitor
6,626 Views
Registered: ‎01-21-2009

Re: About PCI Express example-design

Hi,

Can you please explain me the functionality of the key word - #`TCQ

something <= #`TCQ {*****something****}

Thank you.

Regards,
Gayan
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Xilinx Employee
Xilinx Employee
6,613 Views
Registered: ‎04-16-2008

Re: About PCI Express example-design

TCQ is a delay. Here is how you can determine the length of the delay. In the file PIO_64_RX_ENGINE.v on line 25 = timescale 1ns/1ns, line 27=TCQ 1.

 

Therefore TCQ=1 and the unit delay is 1ns, So wherever you see #`TCQ a delay of 1 ns is asserted by the simulator before the stated action is done.

 

For example ,on line 214  trn_rdst_rdy_n <= #`TCQ 1'b0; means that the value of 0 will be assigned to trn_rdst_rdy_n after 1 ns.

 



  

 

 

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